PIC32MZ System Bus

Last modified by Microchip on 2023/11/09 09:01

system bus overview diagram

The PIC32MZ family of devices incorporates a System Bus, which is implemented as a multi-layer fabric that allows concurrent transactions by multiple initiators (bus masters) to multiple targets (bus slaves). There are no arbitration delays unless two initiators attempt access to the same target at the same time. Initiators include the Central Processing Unit (CPU), general-purpose DMA, and bus master peripherals with dedicated DMA access.

Main Features

  • Runs at SYSCLK speed (200MHz max)
  • Multiple initiators talk to multiple targets
  • Multiple independent transactions per SYSCLK cycle
  • Arbitration takes place for collisions
    • Least-recently serviced initiator wins
    • QOS (quality-of-service) is configurable

Typical single-threaded applications will not need to perform any special initialization of the System Bus registers to obtain these basic features.

  • The presence of large CPU instruction/data cache memory greatly minimizes potential collisions.

Refer to "Section 48. Memory Organization and Permissions" of the PIC32MZ family reference manual (Memory Organization - DS60001214) for a detailed discussion on the System Bus. 

Initiators and Targets

As shown in the PIC32MZ EF Family Block Diagram (see below), there are multiple initiator modules (I1 through I14) in the system that can access various target modules (T1 through T13).

PIC32MZ EF Family Block Diagram

The following table illustrates which initiator can access which target. The System Bus supports simultaneous access to targets by initiators, so long as the initiators are accessing different targets. The System Bus will perform arbitration if multiple initiators attempt to access the same target.

Initiators to Targets Access Association table

Some peripherals are grouped together as a single target to form a Peripheral Bus, which in addition to sharing a target interface, also shares a common peripheral bus clock source (PBCLK).

System Bus latency is therefore determined by:

  • Speed of the target peripheral/bus
  • Collisions/Arbitration Policy

System Bus Arbitration

Two initiators cannot access the same target at the same time. If this occurs, arbitration takes place, which prioritizes the access of the two or more initiators, granting access to one while holding off any others. Arbitration can be minimized or avoided in system design by partitioning SRAM allocation for the CPU and DMA initiators into the two SRAM banks. This also applies to devices where identical peripherals are available on different peripheral buses.

A detailed discussion of arbitration settings is beyond the scope of this tutorial. Refer to "Section 48. Memory Organization and Permissions" of the PIC32MZ family reference manual (Memory Organization - DS60001214) for a detailed discussion.

Access Permissions

The PIC32MZ family of devices provides configurable memory protection features that can be used to restrict access by bus initiators to bus targets or bus target regions. Access violations are logged and can optionally generate interrupts. These features are typically used by operating systems and boot loaders to prevent one task or application from interfering with the execution of another task or application and can also be used to help prevent an untrusted application from accessing protected memory regions for the purpose of intellectual property infringement.

A detailed discussion of access permission settings is beyond the scope of this tutorial. Refer to "Section 48. Memory Organization and Permissions" of the PIC32MZ family reference manual (Memory Organization - DS60001214) for a detailed discussion.