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Step 3: Internal and External Clock Configuration

Last modified by Microchip on 2026/06/22 15:49

Internal Clock Configuration

Launch Clock Easy View by going to the MCC tab in MPLAB® X IDE and then select Plugins > Clock Configuration.

                 Project Graph                     

Click the Clock Easy View tab, then maximize the window by double-clicking on it for a better view.

Clock Easy View 

Configure GCLK Generator 1 and select OSCULP32K as a clock source for GCLK Generator 1.

                                                         GCLK Generator 1

GCLK Generator 1 will then generate a clock signal at 32,768 Hz.

Select the Fractional Digital Phase-Locked Loop (FDPLL) module. Set the clock source to GCLK1 and choose GCLK_DPLL as the input. Click on Auto Calculate and enter the Desired FDPLL Output Frequency as 48,000,000 Hz.

Desired FDPLL Output Frequency              

The FDPLL module will appear as shown in the accompanying image after completing the configuration.

              FDPLL module                                                             

Configure GCLK Generator 0 to use the FDPLL as its clock source.

GCLK Generator 0

After completing the internal clock configuration, proceed to:

  • Step 4: Generate Code
  • Step 5: Add the Application Code to the Project
  • Step 6: Build, Program, and Observe the Output

                     

These steps generate the necessary project files and allow verification of the internal clock configuration by observing the output.

Note: After completing the internal clock configurations and recording the output observations, reconfigure the clock system to use the external clock by applying the specified external clock settings below.

External Clock Configuration

Enable the 32KHz External Crystal Oscillator (XOSC32K) and 32 KHz Output by configuring the 32K Crystal Oscillator as shown in the following configuration image.

                             Crystal Oscillator

In the FDPLL configuration, select XOSC32K as the clock source and deselect the GCLK_DPLL.

                 FDPLL configuration

After completing the configuration, the FDPLL module will be displayed as shown in the accompanying image. 

             FDPLL module

After completing the external clock configuration, proceed to:

  • Step 4: Generate Code
  • Step 5: Add the Application Code to the Project
  • Step 6: Build, Program, and Observe the Output

These steps will generate the necessary project files and enable you to verify the external clock configuration by observing the output. 

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