Arm® Cortex®-M0+ Debug Access Port (DAP)

Last modified by Microchip on 2023/11/09 09:01

The Arm® Cortex®-M0+ Debug Access Port (DAP) enables communication between the core and the device pins during debugging.

The DAP enables the following:

DAP diagram

  • Halting, resuming, and single stepping of program execution
  • Access to processor core registers and special registers
  • On-the-fly memory access
  • Data watchpoints
  • HW/SW breakpoints
  • PC sampling for basic profiling

The Data Watchpoint Unit (DWT) is a debug unit that provides up to 2 watchpoints for data tracing and system profiling (CPU statistics, PC sampler).

The Breakpoint Unit (BPU) allows up to four Hardware breakpoints to generate debug events

The Micro Trace Buffer (MTB) provides a simple instruction trace. It uses a small portion of SRAM for the trace buffer.

The Serial Wire Debug (SWD) port consists of three pins.

DAP pins table

Unlike the other SAM micros, the SAM D, SAM L, and SAM C micros (Cortex-M0+ based) do not implement the JTAG interface. It is SWD only.

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