Arm® Cortex®-M0+ Pipeline

The Arm^® Cortex^®-M0+ core has a two-stage pipeline (Cortex-M0, M3, and M4 have three stages). This two-stage pipeline decreases the core response time and power consumption.

• Stage 1: Fetch & Pre-Decode
• Stage 2: Main Decode & Execute

When older Cortex-M cores (with a three-stage pipe) execute a conditional branch, the next instructions are no longer valid. This means that the pipeline must be flushed every time there is a branch. By moving to a two-stage pipeline, access to Flash is minimized and power consumption is lowered. Flash memory power often contributes the majority of the power consumed in a microcontroller, so any reduction in Flash accesses has a very direct effect on the total power consumed.