SAM L10/L11 Supply Controller (SUPC)

Overview

The Supply Controller (SUPC) manages the voltage reference and power supply of the device. The SUPC controls the voltage regulators for the core (VDDCORE) domain. It sets the voltage regulators according to the Sleep modes, or the user configuration. In Active mode, the voltage regulators can be selected on the fly between LDO (low-dropout) type regulator or buck converter. The SUPC embeds two brown-out detectors. BOD33 monitors the voltage applied to the device (VDD) and BOD12 monitors the internal voltage to the core (VDDCORE). The brown-out detector can monitor the supply voltage continuously (Continuous mode) or periodically (Sampling mode). The SUPC also generates a selectable reference voltage and a voltage-dependent on the temperature that can be used by analog modules like the Analog-to-Digital Converter (ADC) or Digital-to-Analog Converter (DAC).

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Features

• Voltage Regulators System
• Main voltage regulator: LDO or buck converter in Active mode (MAINVREG)
• Low-Power voltage regulator in Standby mode (LPVREG)
• Adjustable VDDCORE to the Sleep mode or the performance level
• Controlled VDDCORE voltage slope when changing VDDCORE
• Voltage Reference System
  • Reference voltage for ADC and DAC
  • Temperature sensor
• 3.3V Brown-Out Detector (BOD33)
  • Programmable threshold
  • Threshold value loaded from NVM User Row at startup
  • Triggers resets, interrupts, or events. Action loaded from NVM User Row
  • Operating modes:
    • Continuous mode
    • Sampled mode for low-power applications with a programmable sample frequency
  • Hysteresis value from Flash user calibration
• 1.2V Brown-Out Detector (BOD12)
  • Internal non-configurable brown-out detector

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Block Diagram

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Principle of Operation

The SUPC bus clock (CLK_SUPC_APB) can be enabled and disabled in the Main Clock module. A 32 kHz clock, asynchronous to the user interface clock (CLK_SUPC_APB), is required to run BOD33 and BOD12 in Sampled mode. Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains.

Interrupts

The interrupt request lines are connected to the interrupt controller. Using the SUPC interrupts requires the interrupt controller to be configured first.

Events

The events are connected to the Event System.

Enable, Disable and Reset

The LDO main voltage regulator is enabled after any Reset. The main voltage regulator (MAINVREG) can NOT be disabled, so the Enable bit in the VREG register (VREG.ENABLE) must always be set to one. The main voltage regulator output supply level is automatically defined by the performance level or the Sleep mode selected in the Power Manager module. After a Reset, the LDO voltage regulator supplying VDDCORE is enabled.

Selecting the Main Voltage Regulator

In Active mode, the type of the main voltage regulator supplying VDDCORE can be switched on the fly. The two alternatives are an LDO regulator and a buck converter. The main voltage regulator switching sequences are as follows:

• Change the value of the Voltage Regulator Selection bit in the Voltage Regulator System Control register (VREG.SEL)
• The start of the switching sequence is indicated by clearing the Voltage Regulator Ready bit in the STATUS register (STATUS.VREGRDY = 0)
• Once the switching sequence is completed, STATUS.VREGRDY will read 1

The Voltage Regulator Ready (VREGRDY) interrupt can also be used to detect a zero-to-one transition of the STATUS.VREGRDY bit.

Voltage Scaling Control

The VDDCORE supply will change under certain circumstances:

• When a new performance level (PL) is set
• When the Standby Sleep mode is entered or left
• When a sleepwalking task is requested in Standby Sleep mode

To prevent high peak current on the main power supply and to have a smooth transition of VDDCORE, both the voltage scaling step size and the voltage scaling frequency can be controlled, VDDCORE is changed by the selected step size of the selected period until the target voltage is reached. The Voltage Scaling Voltage Step field is in the VREG register (VREG.VSVSTEP). The Voltage Scaling Period field is VREG.VSPER. The following waveform shows an example of changing performance level from PL0 to PL2.

Setting VREG.VSVSTEP to the maximum value allows the voltage to transition in one step. The STATUS.VCORERDY bit is set to 1 as soon as the VDDCORE voltage has reached the target voltage. During voltage transition, STATUS.VCORERDY will read 0. The Voltage Ready interrupt (VCORERDY) can be used to detect a 0-to-1 transition of STATUS.VCORERDY. When entering the Standby Sleep mode and when no sleepwalking task is requested, the VDDCORE Voltage scaling control is not used.

Sleep Mode Operation

In Standby mode, the low-power voltage regulator (LPVREG) is used to supply VDDCORE. When the Run in Standby bit in the VREG register (VREG.RUNSTDBY) is written to 1, VDDCORE is supplied by the main voltage regulator. Depending on the Standby in PL0 bit in the Voltage Regulator register (VREG.STDBYPL0), the VDDCORE level is either set to the PL0 voltage level or remains in the current performance level.

By writing the Low-Power mode Efficiency bit in the VREG register (VREG.LPEFF) to 1, the efficiency of the regulator in LPVREG can be improved when the application uses a limited VDD range (2.5 to 3.63V). It is also possible to use the BOD33 in order to monitor the VDD and change this LPEFF value on the fly according to the VDD level.

Voltage Reference System Operation

The reference voltages are generated by a functional block DETREF inside of the SUPC. DETREF is providing a fixed-voltage source, BANDGAP = 1.1V, and a variable voltage, INTREF. The voltage reference output and the temperature sensor are disabled after any Reset. The voltage reference output is enabled/disabled by setting/clearing the Voltage Reference Output Enable bit in the Voltage Reference register (VREF.VREFOE). The temperature sensor is enabled/disabled by setting/clearing the Temperature Sensor Enable bit in the Voltage Reference register (VREF.TSEN).

The Voltage Reference Selection bit field in the VREF register (VREF.SEL) selects the voltage of INTREF to be applied to analog modules (e.g., the ADC).

Low-Power VREF in Active Mode

During active functional mode, the BOD33 and the main Voltage Regulator (VREG) can reduce their power consumption by using a low-power voltage reference (ULPVREF). The low-power voltage reference is started after power-up and is available when the ULPVREFRDY bit in the STATUS register is high. The ULPVREF Ready (ULPVREFRDY) interrupt can also be used to detect a zero-to-one transition of the STATUS.ULPVREFRDY bit. Writing the VREF bit in the BOD33 register to 1 selects ULPVREF as voltage reference for the BOD33. If the chip operates in PL0 (PM->PLCFG.PLSEL = 0) or the Performance Level is disabled (PM->PLCFG.PLDIS = 1), writing the VREFSEL bit in the VREG register to 1 selects ULPVREF as voltage reference for the main voltage regulator.

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Code Example

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