SAM C21 SERCOM SPI Slave Mode Overview

Last modified by Microchip on 2023/11/10 11:08

The SAM C21 family of devices include up to eight instances of the SERCOM serial communication interface peripheral, which among other things, can be configured to be a Serial Peripheral Interface (SPI).

A SERCOM instance can be configured to be either an SPI Master or an SPI Slave. Both master and slave have an interface containing a shift register, a transmit buffer, and two receive buffers. In addition, the SPI Master uses the SERCOM baud rate generator, while the SPI Slave uses the SERCOM address match logic.

This page focuses on the Slave mode of the SERCOM SPI peripheral. Some of the key features of the Slave Mode SPI operation are:

  • Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
  • Single-buffered transmitter, double-buffered receiver
  • Supports all four SPI modes of operation
  • Single data direction operation allows alternate function on MISO or MOSI pin
  • Selectable LSB- or MSB-first data transfer
  • Can be used with DMA
  • Wake on SS transition
  • Optional Addressing Mode:
    • Two unique addresses
    • Address with Address Mask
    • Range of Addresses

samc21 spi slave block diagram

The SPI is a four-wire high-speed synchronous data transfer interface. As the master, the SPI initiates and controls all data transactions. The four communication lines identified in the diagram below are Slave/Chip Select (CS), Master-In-Slave-Out (MISO), Master-Out-Slave-In (MOSI), and Serial Clock (SCK). There are several ways to designate the communication lines used in an SPI connection. For instance, the figure below is taken from a Microchip Technology Inc. EEPROM datasheet and uses CS, SI, and SO while the SAM C21 uses SS, MOSI, and MISO respectively to designate chip to select, master serial data out, and master serial data in lines.

A typical communication transaction is shown in the following image. The master drives the CS Low, the instruction is clocked from the master on the MOSI (SI) line, and data is clocked back to the master on the MISO (SO) line. The Clock line (SCK) is driven by the master.

basic spi master-transaction diagram

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