SAM D21 Digital to Analog Converter (DAC) Overview

Last modified by Microchip on 2023/11/10 11:08

The Digital-to-Analog converter (DAC) converts a digital value to an analog voltage. The SAM DAC module has one channel with 10-bit resolution and is capable of converting up to 350 kilo samples per second (ksps).

A common use of DAC is to generate audio signals by connecting the DAC output to a speaker, or to generate a reference voltage, either for an external circuit or an internal peripheral such as an Analog Comparator (AC).

After being set up, the DAC converts new digital values written to the conversion data register (DATA) to an analog value either on the VOUT pin of the device, or internally for use as an input to the AC, Analog-to-Digital Converter (ADC), and other analog modules.

A simplified block diagram of the DAC can be seen in the accompanying image.

DAC Block Diagram

Conversion Range

The conversion range is between GND and the selected voltage reference. Available voltage references are:

  • AVCC voltage reference
  • Internal 1V reference (INT1V)
  • External voltage reference (AREF)

Internal references are enabled by the driver, but not disabled. Any reference not used by the application should be disabled by the application.

The output voltage from a DAC channel is given as:


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The digital value written to the DATA register will be converted to an analog value. Writing to the DATA register will start a new conversion. It is also possible to write the conversion data to the DATABUF register, the writing of the DATA register can then be triggered by the event system, which will load the value from DATABUF to DATA.

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DAC Output

The analog output value can be output to either the external VOUT pin or internally to a peripheral, but not both at the same time.

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External Output

The output buffer must be enabled in order to drive the DAC output to the VOUT pin. Due to the output buffer, the DAC has high drive strength and is capable of driving both resistive and capacitive loads, as well as loads that combine both.

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Internal Output

The analog value can be internally available for use as input to the AC or ADC modules.

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Events generation and event actions are configurable in the DAC. The DAC has one event line input and one event output: Start Conversion and Data Buffer Empty. If the Start Conversion input event is enabled in the module configuration, an incoming event will load data from the data buffer to the data register and start a new conversion. This method synchronizes conversions with external events (such as those from a timer module) and ensures regular and fixed conversion intervals. If the Data Buffer Empty output event is enabled in the module configuration, events will be generated when the DAC data buffer register becomes empty and new data can be loaded to the buffer.

The connection of events between modules requires the use of the event driver to route the output event of one module to the input event of another. For more information on event routing, refer to the documentation SAM Event System (EVENTS) Driver.

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Left and Right Adjusted Values

The 10-bit input value to the DAC is contained in a 16-bit register. This can be configured to be either left or right adjusted. In the figure below, both options are shown, and the position of the Most Significant Bit (MSB) and the Least Significant Bit (LSB) are indicated. The unused bits should always be written to zero.

Left and Right Adjusted Values

Clock Sources

The clock for the DAC interface (CLK_DAC) is generated by the Power Manager. This clock is turned on by default and can be enabled and disabled in the Power Manager.

Additionally, an asynchronous clock source (GCLK_DAC) is required. These clocks are normally disabled by default. The selected clock source must be enabled in the Power Manager before it can be used by the DAC. The DAC core operates asynchronously from the user interface and peripheral bus. As a consequence, the DAC needs two clock cycles of both CLK_DAC and GCLK_DAC to synchronize the values written to some of the control and data registers. The oscillator source for the GCLK_DAC clock is selected in the System Control Interface (SCIF).

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Special Considerations

Output Driver

The DAC can only do conversions in Active or Idle modes. However, if the output buffer is enabled, it will draw current even if the system is in sleep mode. Therefore, always make sure that the output buffer is not enabled when it is not needed to ensure minimum power consumption.

Conversion Time

DAC conversion time is approximately 2.85 μs. You must ensure that new data is not written to the DAC before the last conversion is complete. Conversions should be triggered by a periodic event from a Timer/Counter or another peripheral.

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