SAM D21 Non-Volatile Memory Controller (NVMCTRL) Overview

Last modified by Microchip on 2023/11/09 09:01

Module Overview

The Non-Volatile Memory (NVM) module provides an interface to the device's Non-Volatile Memory controller, so that memory pages can be written, read, erased, and reconfigured in a standardized manner.

Driver Feature Macro Definition

Driver feature macroSupported devices

The specific features are only available in the driver when the selected device supports those features.

Memory Regions

The NVM memory space of the SAM devices is divided into two sections: The Main Array section, and an Auxiliary space section. The Main Array space can be configured to have an (emulated) EEPROM and/or bootloader section. The memory layout with the EEPROM and bootloader partitions is shown in the figure.

The Main Array is divided into rows and pages, where each row contains four pages. The size of each page may vary from 8-1024 bytes dependent of the device. Device specific parameters such as the page size and total number of pages in the NVM memory space are available via the nvm_get_parameters() function.

An NVM page number and address can be computed via the following equations:

PageNum = (RowNumx4) + PagePosInRow
PageAddr = PageNum ∗ PageSize

Memory Regions

The figure below shows an example of the memory page and address values associated with logical row 7 of the NVM memory space.

memory page address values

Region Lock Bits

As mentioned in Memory Regions, the main block of the NVM memory is divided into several individually addressable pages. These pages are grouped into 16 equal sized regions, where each region can be locked separately issuing an NVM_COMMAND_LOCK_REGION command or by writing the LOCK bits in the User Row. Rows reserved for the EEPROM section are not affected by the lock bits or commands.

By using the NVM_COMMAND_LOCK_REGION or NVM_COMMAND_UNLOCK_REGION commands, the settings will remain in effect until the next device reset. By changing the default lock setting for the regions, the auxiliary space must to be written, however the adjusted configuration will not take effect until the next device reset.

If the Security Bit is set, the auxiliary space cannot be written to. Clearing of the security bit can only be performed by a full chip erase.


Reading from the NVM memory can be performed using direct addressing into the NVM memory space, or by calling the nvm_read_buffer() function.

Writing to the NVM memory must be performed by the nvm_write_buffer() function - additionally, a manual page program command must be issued if the NVM controller is configured in manual page writing mode.

Before a page can be updated, the associated NVM memory row must be erased first via the nvm_erase_row() function. Writing to a non-erased page will result in corrupt data being stored in the NVM memory space.