SAM D21 Power Manager (PM)

Last modified by Microchip on 2023/11/10 11:09

The Power Manager (PM) consists of three modules: the synchronous clock controller, the sleep controller, and the reset controller. These modules are responsible for distributing clocks, supervising low-power modes, and administering the MCU's resets.

The PM is an essential peripheral of an Arm® Cortex®- M0+ MCU and must be configured by the application during startup.

power manager diagram

Clock Distribution

  • The PM receives GCLK_MAIN from GLCK and distributes clocks to the CPU (CLK_CPU), the high-speed bus (CLK_AHB), and the peripheral bus (CLK_APBx).

  • All PM-distributed clocks are derived from GCLK_MAIN.
  • In order to save power, PM-generated clocks can be divided down to a speed slower than GLK_MAIN.
  • The AHB clock is always synchronized, in phase and frequency, with the clock sent to the CPU.
  • Peripheral bus clocks can run at the same speed as the CPU and AHB clocks, however, they are typically pre-scaled to run at a lower frequency.
  • As an additional power-saving feature, the PM uses programmable masks to distribute the AHB, and the APB clocks to a limited number of user-selected peripherals.
  • The PM provides the mechanism for run-time switching of MCU clock frequencies.

cm0plus power manager clock distribution

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Power Management

The PM supervises lower-power STANDBY and IDLE modes.


STANDBY is the lowest power consumption mode available on a SAMD21 MCU. In STANDBY mode, all system clocks are disabled and the voltage regulators are set to run in low-power mode. There are three run-time options for the device's oscillators during STANDBY. The System Controller (SYSCTRL) programs the oscillators for one of these three options:

  • Stop during STANDBY
  • Run during STANDBY
  • Run only if a peripheral requests the oscillator (aka SleepWalking).

A device enters STANDBY when a Wait For Interrupt (WFI) instruction is executed while SCR.DEEPSLEEP is set to '1'.

An interrupt or the Watch Dog Timer (WDT) will cause the device to wake up and resume operation.


IDLE mode stops the CPU clock but leaves the peripherals running. There are three levels of IDLE mode on the SAM D21. The IDLE levels selectively turn off unneeded clocks to save power (see the following table).

The device enters IDLE after executing a WFI instruction with SCR.DEEPSLEEP set to '0' and the sleep level is loaded into SLEEP.IDLE

An interrupt or WDT timeout will cause the device to exit IDLE and return to ACTIVE mode.

cm0plus power manager sleep modes

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Reset Control

The PM supports six reset sources and two modes of reset.

Reset Sources

SAM D21 MCU and most M0+ Microchip MCUs have six possible reset sources:

  1. Power-On reset (POR) occurs on power-up. The device is held in a reset state until power has stabilized throughout the part and a 1 Mhz clock (generated from OSC8M) is available and sent to the CPU.
  2. BOD12 will reset the device if a voltage of 1.2V or below is observed on the I/O pin supplying power to the MCU core (VDDCORE).
  3. BOD33 resets the device if the voltage on the VDDANA pin falls below a value configured by the SYSCTRL
  4. Software Reset occurs when the application code executes a "reset" instruction.
  5. External Reset occurs when the external reset signal is pulled low holding the device in reset.
  6. WDT reset is asserted when the WDT timer has not been cleared by the application software within the allocated time window.

Reset Modes

Resets are divided into two modes based on the source of the reset.

  • Power Resets include resets generated by POR, BOD12, and BOD33.
  • User Resets consist of the external reset, WDT, and the software reset instruction

Both power and user reset causes the device to restart and set most registers of the MCU to a preset state. The difference between the two modes is how they affect the Real Time Clock, the 32 K oscillator, and the WDT. The differences are shown in Table 16.2 of the device datasheet. The underlying reasoning for having two reset modes is to protect the operation of the WDT and the RTC from non-power-related anomalies.

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What Happens at Reset

Upon exiting the reset, the PM receives a 1 Mhz GCK_MAIN from Generic Clock Controller (GLCK). The PM passes this signal to the CPU and a set of pre-determined peripherals.

Refer to the datasheet of the part you are using to see the default state of the peripheral clocks.

It is expected that, during start-up, the CPU will reprogram the speed of PM-generated clocks to achieve the speed needed by the application.

The SAMD21 maintains the source of the latest reset in the RCAUSE register. RCAUSE can be read by the application to determine what recovery or startup actions the application needs to take.

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