SAMD21 System Control Block (SCB) Overview

The System Control Block (SCB) is the programmer's model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions. The SCB registers are:

CPUID Register

The CPUID register contains the processor part number, version, and implementation information.

Interrupt Control and State Register

• The ICSR provides:
  • A set-pending bit for the Non-Maskable Interrupt (NMI) exception.
  • Set-pending and clear-pending bits for the PendSV and SysTick exceptions
• The ICSR indicates:
  • The exception number of the highest priority pending exception.

Vector Table Offset Register

If implemented, the VTOR indicates the offset of the vector table base address from memory address 0x00000000.

Application Interrupt and Reset Control Register

The AIRCR provides endian status for data accesses and resets control of the system.

System Control Register

The SCR controls features of entry to and exit from low power state.

Configuration and Control Register

The CCR is a read-only register and indicates some aspects of the behavior of the Arm^® Cortex^®-M0+ processor.

System Handler Priority Registers

The SHPR2-SHPR3 registers set the priority level (0 to 192) of the system exception handlers that have configurable priority.
SHPR2-SHPR3 are word accessible.