AVR® Interrupts

Last modified by Microchip on 2023/11/09 09:02

AVR® devices provide several different interrupt sources including internal and external interrupts. Interrupts can stop the main program from executing to perform a separate interrupt service routine (ISR). When the ISR is completed, program control is returned to the main program at the instruction that was interrupted.

These interrupts each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written in one logic together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. They have determined priority levels; the lower the address the higher the priority level. RESET has the highest priority, and next is the External Interrupt Request 0 (INT0).

Interrupt Vector Table

Interrupt Vector Table for ATmega324PB

The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register MCUCR. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse.

How it Works

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The interrupt vector directs program control to the proper ISR or execution. That ISR can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. When the ISR is completed and the return (RETI) command is executed from the ISR, the Global I-bit is automatically set to 'ON' and the program execution returns to the main program at the instruction that was interrupted.

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles, the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during the execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.

If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the I-bit in SREG is set.

Additional Information