Optimizing C Code on 8-Bit AVR®

Last modified by Microchip on 2023/11/09 09:02

Before optimizing embedded systems software, it is necessary to have a good understanding of how the AVR® microcontroller (MCU) core is structured.

Optimization Overview

Atmel AVR® 8-bit Architecture

AVR uses the Harvard architecture – with separate memories and buses for programs and data. It has a fast-access register file of 32 x 8 general purpose working registers with a single clock cycle access time. The 32 working registers are one of the keys to efficient C coding. These registers have the same function as the traditional accumulator, except that there are 32 of them. The AVR arithmetic and logical instructions work on these registers, hence they take up less instruction space. In one clock cycle, AVR can feed two arbitrary registers from the register file to the ALU, perform an operation, and write back the result to the register file.

Harvard Architecture

Instructions in the program memory are executed with a single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16 or 32-bit instruction.

The C High-level Language (HLL) has become increasingly popular for programming microcontrollers. The advantages of using C compared to Assembler are numerous: Reduced development time, easier maintainability and portability, and easier-to-reuse. The penalty can be larger code size and as a result of that often reduced speed. To reduce these penalties the AVR architecture is tuned to efficiently decode and execute instructions that are typically generated by C compilers.

Additional Information