How to Implement a Binary Decoder
Overview
A binary decoder translates the values on n input lines into 2n output lines, making it an essential component in various digital systems such as memory address decoding, seven-segment display drivers, keyboard encoding, and data routing systems to select among multiple lines based on a binary input.
The truth table for a 2-to-4 binary decoder is as follows:
| Inputs | Outputs | ||||
| A | B | OUT1 | OUT2 | OUT3 | OUT4 |
| 0 | 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 |
In this table, A and B represent the two input lines, while OUT0, OUT1, OUT2, and OUT3 represent the four output lines. Each output requires an AND gate, and the number of inputs to each AND gate corresponds to the number of input lines in the truth table. For this 2-to-4 decoder example, 4 AND gates, each with 2 inputs, are required.
The diagram demonstrates the implementation of the Boolean expression using the Configurable Logic Block (CLB) module. Typical inputs for a binary decoder include signals from hardware components like switches, GPIO pins, or counters, as well as software-generated signals or clock-driven inputs. These inputs can come from any source that provides binary values for selecting outputs.
Requirements
- Configurable Logic Block (CLB) Peripheral
- Find a Part - Microcontroller and Processor Products Page
Procedure
Follow these steps to configure the AND gates:
Determine the input conditions for each output
The truth table indicates which input conditions activate each output:
- A = 0, B = 0: Output OUT0 is activated (set to 1), while the others are deactivated (set to 0).
- A = 0, B = 1: Output OUT1 is activated.
- A = 1, B = 0: Output OUT2 is activated.
- A = 1, B = 1: Output OUT3 is activated.
Convert input conditions into Boolean expressions
From the input conditions, derive the Boolean expression for each AND gate:
- OUT0 (00): A & B
- OUT1 (01): A & B
- OUT2 (10): A & B
- OUT3 (11): A & B
Implement the CLB Logic
Configure the CLB to implement the 2-to-4 binary decoder circuit. Refer to the block diagram for guidance. This lesson demonstrates a 2-to-4 binary decoder. For decoders with more inputs, n, or different configurations, refer to Step 1 to derive and implement the correct logic for the desired functionality.
Select a Clock Source for the CLB
Any clock source can be used, as the binary decoder operates independently of the clock. The choice of clock will not affect its functionality.
Assign Pins
Connect the decoder's inputs to the desired signal sources (e.g., GPIO pins, software-driven signals, or peripherals), and route the outputs to the appropriate pins or internal connections for further use.
Verify the Design
Use a debugging tool or oscilloscope to confirm that the outputs correctly represent the decoded values based on the input combinations.
Results
The waveform demonstrates the operation of a 2-to-4 binary decoder with two inputs, Input A and Input B, and four outputs: Output 0 to Output 3. Input A toggles at the highest frequency, while Input B toggles at half the frequency. Each output corresponds to a specific combination of the inputs:
- Output 0 is active when Input B = 0 and Input A = 0.
- Output 1 is active when Input B = 0 and Input A = 1.
- Output 2 is active when Input B = 1 and Input A = 0.
- Output 3 is active when Input B = 1 and Input A = 1.
Only one output is active at a time, confirming the correct behavior of the binary decoder.
