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How to Create a Programmable Delay

Last modified by Microchip on 2025/01/02 09:36

Overview

Often a small delay is needed for synthesizing waveforms, updating state machines, or ensuring a signal is valid. There are many ways to create a delay – some require specific configurations of the Configurable Logic Block (CLB) and work over a narrow range, while others are broader, but require use of the hardware peripherals.

Delaying or Synchronizing with Flip-Flops

The simplest delay is to use flip-flops in the CLB. The flip-flops hold the last value until the clock source transitions. This technique is often used in digital logic to synchronize signals to match delays elsewhere in the logic. For this technique, the delay created is ideally the following formula:

\begin{equation} t_{DELAY(IDEAL)} = \frac {N}{f_{CLK}} \end{equation}

With N being the number of flip-flops and fCLK being the frequency of the CLB clock.

However, if the signal arrives right before the active edge of the clock, the delay will be shorter than this. This can be calculated by:

\begin{equation} t_{DELAY(WORST)} = t_{SETUP}+t_{HOLD} + \frac {N-1}{f_{CLK}} \end{equation}

With tSETUP and tHOLD being the setup and hold times of the flip-flops, N being the number of flip -flops, and fCLK being the frequency of the CLB clock source. Note that if the clock period is in the microsecond range or longer, setup and hold times are negligible sources of error.

Additionally, the signal being delayed must have a frequency greater than fCLK to propagate properly through the flip-flops.

Information

Note: The signal being delayed should have a frequency greater than fCLK to ensure it propagates through the flip-flops.

MPLAB Melody CLB Programmable Delay Schematic

Figure 1

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Requirements

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Procedure

Select a Clock Source for the CLB

If the required delays are integer multiples of each other, then select a clock source that runs at this frequency.

For testing, the CLB clock is TMR0 with a period of 100 μs (10 kHz).

Information

Note: TMR0 toggles the state of its output at each clock edge, so the actual CLB clock source frequency should be half the original which is 200 μs (5 kHz).

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Implement the CLB Logic As Needed

For testing, the signal to delay is PWM1, derived from TMR2 at 5 ms period (200 Hz), 50% duty cycle.

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Assign pins to the desired locations.

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Verify the PWM is delayed with a logic analyzer.

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Results

Figure 2 shows the input signal, Signal, to be delayed and synchronized and the delayed signal, Delay, delayed four clock edges and synchronized with the CLB clock. The delay was four clock edges because the circuit used two flip-flops, each delaying the input signal two clock edges for a total of four.

Programmable Delay Output

Figure 2

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Learn More

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