How to Use Verilog Sheets with the Configurable Logic Block (CLB) Synthesizer Tool
Overview
The Configurable Logic Block (CLB) tool offers users two ways to customize their logic, including the use of Verilog sheets. Verilog delivers a powerful and flexible approach, offering precise control over logic design, faster implementation of complex configurations, and easier replication or sharing of designs. This makes it an excellent choice for those who prefer a code-based workflow or require advanced customization for their projects.
Requirements
Procedure
Launch the CLB Synthesizer tool to start a blank design. You can access the tool through the MPLAB® Code Configurator or use the online version CLB Synthesizer online tool.
Navigate to the Document Section and click on the hamburger icon. This will bring up an option to select New Schematic or New Verilog. Select the New Verilog option.
The Synthesizer tool will now prompt you to name your module. Choose a descriptive and meaningful name that reflects the purpose of your design.
A new Verilog sheet will now appear. Use this sheet to write the logic for your application, including defining the necessary inputs and outputs in your Verilog code.
Once you create your Verilog logic, it will appear as a module named after your design in the Modules section of the CLB Synthesizer tool.
Drag and drop your module onto the main CLB schematic sheet. The module includes connection points for its inputs and outputs, which you can configure as needed for your application.
Finally, verify your design by simulating it in the CLB tool or testing it in your target application. Make sure all connections are correct and that the module behaves as expected in your setup.