Data Memory Addressing on the PIC16F1 MCU

Last modified by Microchip on 2024/02/06 09:24

Contents

Direct Addressing

‍When addressing memory directly, the Effective Address is calculated using two pieces of information:

  1. The run-time content of the Bank Select Register (BSR)
  2. The executing instruction's 7-bit operand

example calculation fo the effective address

another example of direct address calculation

​Assembly language programmers must ensure that the BSR is loaded with the proper bank number for the desired memory location. The assembly language instruction MOVLB is the instruction specifically provided by the MPASM™ assembler for loading the BSR. The assembler DIRECTIVE banksel can also be used to load the BSR. At compile time, the banksel determines the bank of the desired memory location, then configures the MOVLB instruction appropriately for the bank.

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Example code

The following code shows two methods of loading the BSR in assembly language. The first example uses banksel to automatically calculate the BSR. The second example manually calculates the appropriate BSR value.

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banksel  TRISC    ; set BSR to the bank with TRISC
clrf     TRISC    ; clear TRISC  
molvb  2         ; load BSR with the literal value 2
clrf    LATC     ; clear  LATC

​Users of the MPLAB® XC8 C Compiler do not need to be directly concerned with banking. Assignment statements will result in the compiler and linker calculating and inserting the needed MOLVB instructions.

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Indirect Addressing

Indirect Addressing Registers

Enhanced Mid-Range PIC® MCUs have two channels that indirectly access data memory. Each channel uses three core registers to implement indirect addressing.

FSR0L, FSR0H, and INDF0 control channel 0.

FSR1L, FSR1H, and INDF1 control channel 1.

indirect registers

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Register Usage

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR1H/FSR1L or FSR0H/FSR0L)

To access an address indirectly: first write the address into FSRn, then execute an instruction with INDFn as the operand.

Sample Code using Indirect Addressing

assembly code using indirect addressing

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Indirect Addressing Modes

The FSR registers form a 16-bit address that allows an address space with 65536 possible values. Depending on the value placed in FSRn registers, a PIC16F1xxx MCU will access the memory in one of three different modes:

traditional data memory access

Traditional Data Memory Access

When the value of FSRn is between 0h and FFFh instructions using INDFn will access the memory in the Traditional Access Method. In this mode of operation all memory locations including Special Function Registers, General Purpose RAM, and the Common memory are accessable through INDFn.

linear data memory access

Linear Data Memory Access

Each memory bank contains 80 bytes of general purpose memory (addresses 20h-6Fh). When the application requires an array or buffer of data which exceeds 80 bytes, traditional indirect access may not provide convenient interface to the data structure. The linear addressing method is designed to handle data structures larger than 80 bytes.

When FSRxH<7:5> contains '001' the general purpose sections of the data banks are accessed as if they were one contiguous memory block. When an FSR is incremented beyond the GPR limit of a bank, the GPR memory of the next bank is automatically accessed making the entire GPR memory appear as one contiguous block.

program memory acess

Program Memory (FLASH) Access

To make constant data access easier, the entire program Flash memory can be mapped to the FSR space. When Bit7 of the FSRxH register is set, the remaining 15 bits of FSR point to an address in Program memory. In the Program Memory mode the MCU's Flash memory contents can be read, but not altered. When accessed, only the lower 8 bits of the program memory are read. Access to an unimplemented memory address will always return a '0'.

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