8-bit PIC® MCU Low Power Terminology
Last modified by Microchip on 2024/09/25 13:46
Terminology
| CPU (Central Processing Unit) | The primary component of the microcontroller that performs calculations and executes instructions. |
| Data Memory | The memory area where variables and data are stored during program execution. In this training, it is analogous to RAM. |
| DSBOR (Deep Sleep Brown-Out Reset) | A reset triggered by low voltage conditions while the microcontroller is in Deep Sleep mode. |
| DSWDT (Deep Sleep Watchdog Timer) | A watchdog timer specifically designed for low-power sleep modes. |
| FOSC | The frequency at which a microcontroller's primary clock operates, affecting its processing speed. |
| GIE (Global Interrupt Enable) | A control bit that enables or disables all interrupt sources in a microcontroller. |
| GIEL/H (Global Interrupt Enable Low/High) | Specific settings to enable or disable low-priority or high-priority interrupts. |
| GPIO (General Purpose Input/Output) | Pins on a microcontroller that can be configured as either input or output for various functions. |
| INTRC (Internal Oscillator) | An internal clock source within a microcontroller that can be used for timing functions. |
| INT0 | An external interrupt source that can trigger an interrupt service routine based on external events. |
| IOC (Interrupt-On-Change) | A feature that allows GPIO pins to generate interrupts when their state changes. |
| ISR (Interrupt Service Routine) | A special function that executes in response to an interrupt, allowing the microcontroller to react to events. |
| LDO (Low Dropout Regulator) | In this training, refers to the internal regulator used to produce Vddcore voltage. |
| LPBOR (Low Power Brown-Out Reset) | A reset feature that triggers when the supply voltage drops below a certain threshold during low-power operation. |
| MCLR Reset | A reset pin that, when activated, resets the microcontroller to a known state. |
| MCU (Microcontroller Unit) | A compact integrated circuit designed to govern a specific operation in an embedded system, containing a CPU, memory, and peripherals. |
| PFM (Program Flash Memory) | Non-volatile memory the CPU uses to fetch instructions or store data. |
| PMD (Peripheral Module Disable) | A feature used to enable or disable peripheral modules in a microcontroller to save power. |
| POR (Power-On Reset) | A feature that ensures the microcontroller starts in a defined state when power is applied. |
| Program Counter | A register that holds the address of the next instruction to be executed by the CPU. Its value is stored as SFR locations that can be read and written. |
| RAM (Random Access Memory) | A type of volatile memory used to store data temporarily while a microcontroller is powered on. In this training, it is analogous to Data Memory. |
| RTCC (Real-Time Clock Calendar) | A device that keeps track of the current time and date, even when the main power is turned off. |
| SFR (Special Function Register) | A register in a microcontroller that controls specific functions or features, such as I/O operations. |
| TRIS (Tri-state Control Register) | A register used to configure the direction (input/output) of GPIO pins on a microcontroller. |
| ULPWU (Ultra Low Power Wake-Up) | A feature that allows a microcontroller to wake up from low-power modes efficiently using an external charging capacitor. |
| Vddcore | The internal regulator’s output voltage used to power the CPU and PFM. It is typically set at a lower voltage than Vdd to conserve power. |
| WDT (Watchdog Timer) | A timer that automatically resets the system if the software fails to reset it, ensuring reliability in embedded applications. |
| WWDT (Windowed Watchdog Timer) | A watchdog timer that requires the software to reset it within a defined window of time to avoid system resets. |