CCP/ECCP Compare I/O Pin Configuration

Last modified by Microchip on 2023/11/10 11:10

The software design must configure the CCPx pin as an output for the Compare mode by clearing the associated TRIS bit. On some newer devices, the CCPx pin function can be moved to alternative pins using the APFCON0 or APFCON1 registers while on others, it can be moved through the Peripheral Pin Select feature.