Configurable Logic Cell (CLC)

Last modified by Microchip on 2023/11/09 09:03

The Configurable Logic Cell (CLC) provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 16 input signals and through the use of configurable gates, reduces the 16 inputs into four logic lines that drive one of eight selectable single-output logic functions.

Input sources are a combination of the following:

  • I/O pins
  • Internal clocks
  • Peripherals
  • Register bits

The output can be directed internally to peripherals and to an output pin.

Possible configurations include:

  • Combinatorial Logic
    • AND
    • NAND
    • AND-OR
    • OR-XOR
    • OR-XNOR
  • Latches
    • S-R
    • Clocked D with Set and Reset
    • Transparent D with Set and Reset
    • Clocked J-K with Reset

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CLC Video Tutorial

This video introduces the Configurable Logic Cell (CLC) for Microchip 8-bit MCU devices and shows how to use it.

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CLC Setup

The CLC peripheral has four sections that need to be set up before it can be used. This involves setting up eight registers in your software program. Once these registers are set up, the CLC will run independently of software control until the registers are changed via software.

They include:

  • CLCxSEL0
  • CLCxSEL1
  • CLCxGLS0
  • CLCxGLS1
  • CLCxGLS2
  • CLCxGLS3

A PIC® device can have multiple CLCs so each CLC module has its own set of eight registers. The x in the register names above represents the CLC number (e.g., CLC1 uses the CLC1CON register).

To simplify the setup, the CLC can be broken down into four sections that need to be configured. They include:

  • Inputs
  • Data Gating
  • Logic Function
  • Output Setting

CLC setup

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Inputs can come from 8-16 different sources, depending on the PIC device, and from this list, up to four can be chosen to feed the data gating section.
They can include:

  • I/O pins
  • Internal clock outputs
  • Peripherals outputs
  • Register bits

The inputs are selected by bits in the CLCxSEL0 and CLCxSEL1 registers.

CLC SEL registers

Each input has an associated 3-bit code that is placed in the CLCxSEL registers to enable the input.

CLC inputs

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Data Gating

The Data Gating section has four logic gates that need to be set up. This requires five separate registers to be set up. They configure the inverted or non-inverted connection from the inputs that control the CLC peripheral. The five registers include:

  • CLCxGLS0
  • CLCxGLS1
  • CLCxGLS2
  • CLCxGLS3

Each gate starts off as a base OR gate, but each input and output can be individually inverted or not inverted.
This allows AND, NAND, OR, and NOR gates to be created. The gates can also be set up to drive a constant 1 or 0 logic level.

Data gating

Each input to a data gate has a pair of bits in one of the CLCxGLSx registers. The two bits include a non-inverted (T) bit and an inverted (N) bit that needs to be set up. If the T bit is set, then the input is non-inverted. If the N bit is set, then the input is inverted. If both are set to zero, then the input is not connected to the gate.

CLC GLS registers

The CLCxPOL register bit, LCxGxPOL bit, will invert or not invert the output of the gate.
0 - non-inverted
1 - inverted

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Logic Function

The Logic Function has eight options to choose from. It is selected in the CLCxCON register. Each Logic Function has a 3-bit code associated with it.

Logic Function

Logic Function

The 3-bit code is set in the CLCxCON register LCxMODE bits to enable the selected Logic Function.

CLCxCON register LCxMODE bits

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All of the CLC sections reduce down to a single output that can drive an I/O pin, feed another CLC module or internal peripheral, or can also trigger a rising or falling edge interrupt. These various options are set up in the CLCxCON and CLCxPOL registers.

There are multiple bits that control the output from the CLC module

The bits in the CLCxCON register control the output settings.

LCxEN – CLC module enable bit (1 - CLC On, 0 - Off )
LCxOE – Output enable bit (1 – Enable, 0 – Disable)
LCxOUT - Internally monitor output via software (Read Only Bit)
LCxINTP – Rising edge interrupt enable (1-CLCxIF set on Rising Edge)
LCxINTN – Falling edge interrupt enable (1-CLCxIF set on Falling Edge)

The bits in the CLCxCON register control the output settings

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CLC Example

Here is a simple example that shows the eight registers set up in software to create the CLC setup shown in the accompanying image.

Eight registers set up in software to create the CLC setup

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CLC Designer Tool

The CLC Designer Tool is a GUI-based tool that makes creating the CLC structure much easier. Through a series of setup options, the tool will automatically output the eight register settings so you can include it in your MPLAB® X project.

The CLC Designer Tool is part of MPLAB Code Configurator (MCC) MPLAB X Plugin.

The CLC Designer Tool is a GUI-based tool

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