EUSART/AUSART: Enhanced-Addressable-Universal-Asynchronous-Receiver-Transmitter

Last modified by Microchip on 2023/11/09 09:03

The Enhanced/Addressable Universal Asynchronous Receiver Transceiver (EUSART/AUSART) is a peripheral for handling serial I/O communications. It contains all the clock generators, shift registers, and data buffers necessary to perform an input or output serial data transfer independent of the main program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system.

  • Full-Duplex mode is useful for communications with peripheral systems such as terminals and personal computers.
  • Half-Duplex Synchronous mode is intended for communications with peripheral devices such as A/D or D/A integrated circuits, serial EEPROMs, or other microcontrollers.

These devices typically do not have internal clocks for baud rate generation and require the external clock signal to be provided by a master synchronous device.

The EUSART module includes the following capabilities:

  • Full-duplex asynchronous transmit and receive
  • Two-character input buffer
  • One-character output buffer
  • Programmable 8-bit or 9-bit character length
  • Address detection in 9-bit mode
  • Input buffer overrun error detection
  • Received character framing error detection
  • Half-duplex synchronous master
  • Half-duplex synchronous slave
  • Programmable clock polarity in synchronous modes
  • Operation in Sleep mode

The EUSART peripheral also implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems:

  • Automatic detection and calibration of the baud rate
  • Wake-up on Break reception
  • 13-bit Break character transmit


Serial Communication is a way to send data between two electronic devices using just two wires. The EUSART/AUSART transmits and receives data using the standard Non-Return-to-Zero (NRZ) format. NRZ is implemented with two levels: a Voltage Output High (VOH) or mark state which represents a 1 data bit, and a Voltage Output Low (VOL) or space state which represents a 0 data bit. NRZ refers to the fact that consecutively transmitted data bits of the same state stay at the same output level without returning to a zero or neutral level between each bit transmission. The Idle state puts the output pin at a mark (i.e., high state). Transmission can occur in a synchronous or asynchronous fashion.

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Synchronous serial communications are typically used in systems with a single Master and one or more Slaves. The Master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the Master clock by eliminating the internal clock generation circuitry.

There are two signal lines in Synchronous mode:

  • A bidirectional data line
  • A clock line

Slaves use the external clock supplied by the Master to shift the serial data into and out of their respective receive and transmit registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that Master and Slave devices can receive and transmit data but not both simultaneously. The EUSART/AUSART can operate as either a Master or Slave device. Start and Stop bits are not used in synchronous transmissions

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In asynchronous communications, two pins are used. One is the Transmit (Tx) and one is the Receive (Rx). The Tx of one device is connected to the Rx of the second device. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator.

There are many formats for asynchronous serial communication and a popular one is the RS-232 standard. RS-232 contains a Start bit followed by a group of data bits and then one or two Stop bits, depending upon the setup. A common setup is 8N1 which means one Start bit, EIGHT data bits, No parity bits, and then ONE Stop bit. No parity information is included which is just a simple way to check for bit errors.

The eight data bits can form 256 different combinations and those combinations are pre-assigned according to the American Standard Code for Information Interchange (ASCII) chart. Each letter, both upper and lower case along with the special characters found on a computer keyboard, each has a unique ASCII code. This allows the microcontroller to transfer text messages as digital data that can be interpreted and converted back to characters as the receiving end.

The EUSART/AUSART transmits and receives the Least Significant Bit (LSb) first. The EUSART/AUSART’s transmitter and receiver are functionally independent but share the same data format and baud rate. An odd or even parity can be determined from the total of the transmitted bit but is not supported by the hardware. It can be implemented in software and stored as the ninth data bit.

There are other standards as well such as Local Interconnect Network (LIN), 9-bit character data, and others. Any of these can be created in software but that would take up a lot of processing time so having a dedicated hardware circuit to handle a majority of the operation can make the application run faster and more reliably.

The EUSART/AUSART peripheral in the PIC® MCU has register buffers for storing the data to be sent (TXREG register) and the data that is received (RCREG register).

Timing is critical for this serial communication so a common baud rate or bits per second timing is established between the two communicating devices. Automatic baud rate detection is built into most EUSART/AUSART peripherals.

The operation of the EUSART module is controlled through three registers:

  • Transmit Status and Control (TXSTA)
  • Receive Status and Control (RCSTA)
  • Baud Rate Control (BAUDCON)
Transmit Block Diagram

Transmit Block Diagram

Receive Block Diagram

Receive Block Diagram

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Baud Rate Calculation

The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART (Universal Synchronous/Asynchronous Receiver/Transmitter) operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode.

The SPBRGH:SPBRG register pair determines the period of the free-running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCON register. In Synchronous mode, the BRGH bit is ignored.

It may be advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies.

Writing a new value to the SPBRGH:SPBRG register pair causes the BRG timer to be reset (i.e., cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock.

The baud rate equations are shown in the chart below. The equation is based on the settings in the BAUDCON register.

baud rate equations

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Example Baud Rate Calculation

For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:

Example Baud Rate Calculation

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