Timer 0 Counter Mode

Last modified by Microchip on 2023/11/22 16:33

Counter Mode

In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI I/O pin. This allows the PIC® MCU to count pulses from an external clock source. The signal has voltage limits as specified in the device datasheet but will typically be the limits of the device's operating voltage.

By selecting this externally triggered counting option to Timer0, the software can monitor the pulses from an external sensor to capture data. Timer0 has a 255 count limit before overflowing back to zero. This count can be extended by using a prescaler.

Counter Setup

8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to 1.

TMR0 Clock

The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION_REG register.

Source Edge Select

Counter Mode Synchronization

When an external clock input is used for Timer0, it must meet certain timing requirements. These requirements ensure the external clock can be synchronized with the internal instruction clock. Also, there may be a slight delay in the actual incrementing of Timer0 after synchronization.

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output. The T0CKI signal has to be at a high level for at least two clock periods of the system clock (Fosc) and a small RC delay of 20 nanoseconds. The signal must also be low for at least two Fosc clock periods.

When a prescaler is used, the external clock input is divided by an asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external TOCKI input to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for the T0CKI signal to have a period of at least four clock periods of the Fosc clock (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse-width requirement for the device (around 10 nanoseconds).