dsPIC33A Hardware Configuration
Overview
Software needs hardware!
Before you can develop firmware with dsPIC33A in MPLAB® X IDE, you need to develop a functional hardware schematic and understand some basic hardware configuration defaults, so your firmware can successfully execute on the target.
This page reviews the required dsPIC33A basic pin connections, and where to locate this information in the device datasheet. We’ll also review the clock system default configuration, and other hardware defaults and how to set configuration bits in C-code to change these default hardware settings.
Required Pin Connections
VDD/VSS & AVDD/AVSS
All VDD/VSS pins must be properly biased with the required supply voltages. This includes the AVDD/AVSS pins, even if no analog functionality is used in your application.
Decoupling capacitors are recommended for use on every pair of VDD/VSS and AVDD/AVSS pins. Refer to the datasheet for details on the recommended values.
MCLR
The MCLR pin is used to perform a device reset and is also used in programming/debug operations.
A pull-up connection to the reset or MCLR (Master Clear) pin is required to keep the device in a normal (non-reset) state. This can be as simple as a 4.7k to 10k pullup resistor from the MCLR pin to VDD but the recommended option is to use an RC circuit (10k and 0.1 uf) from VDD to ground with a small value series resistor (100 to 470 ohm) from the center of the RC connection to the MCLR pin. This will give a slower rise time on the MCLR pin and allow more time for VDD to stabilize.
The series resistor limits current flow into the MCLR in the event of an internal MCLR pin breakdown.
PGC/PGD
Programming and debugging connections, also known as the ICSP (In-Circuit Serial Programming) connections are only required for firmware development and not the operation of the device.
There are five connections required to connect the Programmer/Debugger tool (such as a PICkit™ 5) to the device. These five connections include:
- The VDD and VSS pins
- The MCLR pin
- Plus the ICSP pins: PGC (Clock) and PGD (Data).
Optionally, you can also connect the dsPIC33A serial Universal Asynchronous Receiver Transmitter (UART) TX and RX pins to the PICkit 5 pin header, since this debugger additionally enumerates a USB CDC connection so serial data can be exchanged between the dsPIC® device and a Terminal application running on the PC.
Clock System Configuration
The dsPIC33A clock system supplies clocking to the CPU and peripherals. The module is based on a number of clock generators (CLKGENs) and PLL generators (PLLGENs). The CLKGENs are preassigned to the CPU and peripherals. Each clock generator selects a clock source from the available oscillators or PLLs and passes it to a selectable divider circuit. CLKGEN1 provides the CPU and Peripheral Clocks.
Default Configuration
On reset, CLKGEN1 is enabled with the 8 MHz FRC oscillator source. This provides an 8 MHz clock for the CPU, and 8, 4, and 2 MHz clocks for the Fast, Standard, and Slow peripheral clocks respectively after reset.
For more details, visit the dsPIC33A Clock System page.
Configuration Bits
It is unlikely that a new C program will run properly on the device, even though the program is valid.
All Microchip microcontrollers must be configured to ensure correct hardware operation. Some device configuration settings affect the fundamental operation of the device, such as those controlling the instruction clock. The configurable hardware options are in the datasheet chapter titled “Configuration Bits.”
To configure the device, the programmer must use a series of #pragma config configuration options as shown here:
MPLAB X IDE provides a graphical view to configure and then generate the complete list of #pragma statements which you can copy/paste into your source code:
