dsPIC33A Direct Memory Access (DMA) Controller
Overview
The Direct Memory Access (DMA) controller handles high data throughput peripherals on the Special Function Register (SFR) bus by enabling direct access to data memory to reduce the need for intensive CPU management. The DMA controller is structured with multiple channels, each of which can be connected to a selectable peripheral module. When a peripheral module triggers its interrupt, the corresponding DMA channel responds by accessing the SRAM without requiring CPU intervention.
By offloading the data transfer tasks from the CPU, the DMA controller significantly contributes to improved system functionality and reduces power in various applications.
Features
- Six independent channels
- Concurrent operation with the CPU
- DMA bus arbitration using fixed priority and round-robin scheme
- Four address modes
- Four transfer modes
- Ping-pong mode
- 8-bit, 16-bit or 32-bit word support for data transfer
- 24-bit source and destination address register for each channel, dynamically updated and independently reloadable
- 32-bit transaction count register, dynamically updated and independently reloadable
- Upper and lower address limit registers
- Counter half/full level interrupt
- Software triggered transfer
- Null Write mode for symmetric buffer operations
- DMA request for each channel can be selected from any supported interrupt source
- Support for daisy chaining of channel called channel chaining
- Set/clear/invert bit manipulation capability
- Pattern match
- Bus read/write error fault indication
Architecture
Conceptually, the DMA controller functions both as a peripheral and a direct extension of the CPU. It is located on the microcontroller data bus between the CPU and DMA-enabled peripherals, with direct access to data space (data RAM):
This partitions the SFR bus into two buses, allowing the DMA controller access to the DMA-capable peripherals located on the new DMA SFR bus. This also lowers bus loading for less power consumption per access. The controller serves as a host device on the DMA SFR bus, controlling data flow from DMA-capable peripherals. When the CPU is servicing peripherals that are not on the DMA bus, the DMA controller is free to service peripherals on the DMA bus while the CPU is performing its operations. In this way, the effective bandwidth for handling data is increased. At the same time, DMA operations can proceed without causing a processor stall. When the CPU and DMA are accessing the SFR simultaneously, the CPU gets priority and the DMA will have to wait until the CPU completes the task.
DMA Channel Controllers Block Diagram
The DMA Controller itself is composed of multiple independent DMA channel controllers or simply channels.
Each channel can be independently programmed to transfer data between different areas of the data space, move data between single or multiple addresses, use a wide range of hardware triggers to initiate transfers and conduct programmed transactions once or many times. Multiple channels may even be programmed to work together to carry out more complex data transfers without CPU intervention. The top-level controller sets the boundary addresses for all DMA operations, regardless of the channel. It also arbitrates data bus access between the channels based on a user-selectable priority scheme and determines how DMA will operate in power-saving modes.
DMA Operation
Each channel in the DMA controller may be configured to transfer data from a source address (DMAxSRC) to a destination address (DMAxDST) upon the receipt of a hardware or software trigger. The trigger sources are generally device-level interrupts from peripheral modules, as well as the external interrupts and interrupt-on-change sources. Each DMA channel can handle 8-bit, 16-bit, and 32-bit transactions, and may assert an interrupt to indicate the end of a transfer and/or the status of a transfer in progress.
Types of Data Transfers
All DMA transactions occur solely within the data space address space; this includes the entire SFR space and (by extension) all peripherals.
As defined by the source and destination, there are four types of DMA data transfers:
- Peripheral to Memory (Receive)
- Memory to Peripheral (Transmit)
- Memory to Memory
- Peripheral to Peripheral
There are four transfer modes, which are defined by the number of data transfers that can occur per trigger event, how events are counted, and if the event repeats:
- One-shot
- Repeated one-shot
- Continuous
- Repeated continuous
There are also four addressing modes, providing the necessary automatic source and destination address update options to implement the data transfer types shown above:
- Fixed Address to Fixed Address
- Fixed Address to Block Address
- Block Address to Fixed Address
- Block Address to Block Address
Ping-Pong Mode
The DMA controller supports ping-pong operation to assist the CPU in effective and uninterrupted data transfer. By alternating the incoming data flow between two active DMA channels, the CPU can process the available data from one DMA channel while the other active DMA channel is making its own data available to be processed when the CPU has completed its current task.
Ping-Pong Data Transmit
In this configuration, the DMA controller alternates transmission of outgoing data from two different buffers to a peripheral:
Ping-Pong Data Receive
In this configuration, the DMA controller alternates reception of incoming data between two memory buffers:
Pattern Match
When the content of the incoming data is required in making decisions in real time, the DMA controller can recognize a data pattern in its internal buffer being transferred from the source to the destination locations. The pattern match capability, when enabled, allows a user-programmable data pattern to be compared against a (partial) content of DMABUF[31:0]. Upon match detection, the DMA controller invokes its interrupt to inform the CPU to take further action. This feature is implemented with control, status and pattern with its corresponding mask registers, along with digital control and comparator units, as shown:
Channel Chaining
Channel chaining is used to chain two or more channels together such that once one channel in the sequence, often referred to as the initiating channel, completes its designated task and sets its DONE flag, it sends a signal indicating completion. This signal acts as a trigger for the subsequent channel, known as the chained channel.
Bit Manipulation
The 32-bit DMA controller can perform real-time bit manipulation on the 32-bit data word being moved from the memory-mapped source to the destination location. The bit manipulation is made up of invert, clear and set functions, connected with their associated mask register, and daisy-chained together. Note that each DMA channel is equipped with a one-bit manipulation logic block, and bit manipulation is applied to the DMABUF[31:0] bits during the write cycle, when the data are being stored to the destination location, once the bandwidth has been allocated to the requesting DMA channel.
For more details on DMA configuration and examples, please review the device-specific data sheet.