dsPIC33A Hardware Architecture

Last modified by Microchip on 2025/02/03 14:00

System Block Diagram

dsPIC33A devices contain Digital Signal Processor (DSP) functionality within a high-performance microcontroller (MCU) architecture and include a single and double Precision Floating Point Unit (FPU).

System block diagram

The following subsystems work together to achieve a high-performance embedded controller:

dsPIC33A Core

The dsPIC33A core contains a 32-bit Central Processing Unit (CPU), which runs up to 200 MHz. A 5-stage instruction pipeline is deployed to match the CPU speed to slower Flash program memory. A dedicated hardware floating point co-processor unit is available to speed up arithmetic with real numbers. Multiple data memory bus interfaces facilitate efficient computation of sum-of-products algorithms for DSP applications.

Memory Organization

The memory space of the dsPIC33A is organized into Special Function Register (SFR) memory space, X Data RAM, Y Data RAM, configuration memory space, and user program memory. The allocation of memory space is controlled by the system Bus Fabric (BMX), which handles redirection of code or data access to the appropriate memory interface, thereby creating a unified memory interface for the developer.

Clock System

The dsPIC33A provides a flexible clock system that supplies clocking to the CPU and peripherals. The module contains several clock generators (CLKGENs) and PLL generators (PLLGENs).

Prefetch Branch Unit (PBU)

The Prefetch Branch Unit (PBU) accelerates the interface between the dsPIC33A program Flash memory and the CPU instruction bus. The PBU can predictively prefetch the next sequential address and cache fetched program data that are the target of a CPU instruction fetch. Initial PBUs contain a 2 kB direct-mapped instruction cache.

Exception Mechanism

The dsPIC33A family exception mechanism reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the CPU. The core supports a prioritized interrupt and trap exception scheme.

System Level Improvements

The following table highlights some high-level improvements over our existing dsPIC33C device family:

 Feature/Family  dsPIC33C  dsPIC33A  Advantages
CPU Speed 100 MHz 200 MHz Improved DSP performance (2x faster plus 32-bit precision!)
Memory Map Separate Flash and data Unified (16 MB) Simplifies coding
Memory Addressing Paged Linear Simplifies coding
Floating Point Arithmetic Software Library Hardware FPU Fast computation with real numbers
Data/Instruction Word Size 16-bit/24-bit32-bit/16-bit or 32-bit

Increased precision

Memory efficiency

Instruction Execution from RAM N/A Available 

Improved Latency

Execute from RAM during Flash Update

 Bus Fabric N/A Available Enables a unified memory interface for programming
 Working Registers x Shadow Register Sets 16 x 16-bit x 5 16 x 32-bit x 7 More available dedicated ISR contexts
 Accumulators x Shadow Register Sets 2 x 40-bit x 5 2 x 72-bit x 7 More available dedicated ISR contexts
 Core Voltage 1.2V 1.1V Lower power/MHz

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