dsPIC33A Memory Organization
Overview
The dsPIC33A contains several distinct memory spaces. The allocation of memory space is controlled by the System Bus Fabric (BMX), which handles redirection of code/data access to the appropriate memory interface, creating a unified, non-overlapping 24-bit addressable (16MB) memory map.
Memory Architecture
The memory space of the dsPIC33A is organized around five major regions:
- Special Function Register (SFR)
- X Data RAM (XRAM)
- Y Data RAM (YRAM)
- Configuration Register
- User Program Memory
SFR Memory
The SFR is split into groups based on the bus speed at which they operate. Infrequent access and initialization SFRs are on the "Slow" bus, whereas critical control loop type SFRs are accessed at full speed (relative to the CPU) using the "Fast" bus.
Each peripheral bus speed includes an associated peripheral clock, which is provided by the Peripheral Clock Divider:
- The "Fast Speed" peripheral clock is equal to the CPU or system clock provided by CLKGEN1.
- The "Standard Speed" peripheral clock is equal to half the CPU clock.
- The "Slow Speed" peripheral clock is equal to one-quarter the CPU clock.
Peripheral Bus Speed to Peripheral Mapping Example (dsPIC33AK128MC106)
Data Memory
dsPIC33A devices contain two equal-sized banks of data memory called X RAM and Y RAM. The data memory is accessed using dedicated X and Y Address Generation Units (AGUs) and separate data paths. The BMX handles the redirection of data memory accesses, allowing data memory to be accessed as one linear non-overlapping address range.
Data reads and writes for MCU class instructions always access the X and Y data spaces as a single combined data space.
Dual source operand DSP instructions, such as the MAC instruction, access the X and Y data spaces separately to support simultaneous reads for the two source operands.
Near Data Memory
A 64 KB address space, referred to as near data memory, is reserved in the data memory space between 0x000000 and 0x010000. Near data memory is directly addressable through a 16-bit absolute address field within all file register instructions. The memory regions included in the near data region will depend on the amount of data RAM implemented for each dsPIC33AK device variant.
- For devices that have smaller amounts of data memory, the near data region can include all of X memory space and possibly some or all of Y memory space.
- For devices that have larger amounts of data memory, the near data region can include all of X memory space and possibly some or all of Y memory space.
Configuration Memory
The next region we have is the calibration and configuration region, which is nonvolatile memory.
It includes a calibration section with a Unified Device ID, as well as a customer One-Time-Programmable Memory (OTP) memory. It also includes registers used for calibration that the user can copy for compensation, such as DAC INL and DNL and op amp compensation.
We then have user configuration pages, UCA1 and UCB. UCA1 contains the configuration bits for the device’s operation. UCB contains the configuration bits for the security features.
Finally, we have user configuration page UCA2 available in dual partition devices.
Program Memory
Finally, we have user program memory beginning at address 0x800000, as well as a movable interrupt vector table (IVT). Program memory is read linearly, like data memory, using the MOV instruction.
