dsPIC33A Prefetch Branch Unit (PBU)

Overview

The Prefetch Branch Unit (PBU) in dsPIC33A core devices accelerates the interface between the dsPIC33A program Flash memory and the Central Processing Unit (CPU) instruction bus. The PBU can predictively prefetch the next sequential address and cache fetched program data that are the target of a CPU instruction fetch.

The PBU in dsPIC33A core devices supports the following functions:

• An instruction stream buffer accelerates the execution of linear program code flow.
• An instruction cache accelerates the execution of non-linear program flow changes (branches).

The PBU block diagram, Figure 1, shows data paths to and from the PBU in the dsPIC33A environment. The PBU provides data when the CPU fetches program data from Flash memory. It may provide program data from an internal buffer, or it may fetch program data from Flash if the requested program data is unavailable. Consequently, Flash fetch operations are accelerated when data are sourced from internal PBU buffers.