dsPIC33A Analog-to-Digital Converter (ADC) Peripheral

Overview

This page will teach you about the high-performance dsPIC33A Analog-to-Digital Converter (ADC) designed for advanced embedded control systems. The dsPIC33A ADC stands out for its speed, flexibility, and accuracy, making it ideal for applications like motor control, power conversion, and sensor interfacing.

The dsPIC33A ADC can convert analog signals at up to 40 million samples per second (Msps) per core, with up to five cores available in some devices. It supports up to 20 conversion channels and 26 analog input pins, with any input assignable to any channel. Each channel can be set for single-ended or true differential measurement, and internal sources like a reference voltage or temperature sensor can also be measured.

Sampling and triggering are highly flexible. Each channel can have its own sampling time and trigger source, which can be software, timers, or other device modules. The order and priority of conversions are programmable, allowing precise control for your application.

The ADC supports several operation modes, including single conversion, integration (accumulating samples for noise reduction), oversampling (for higher resolution), and gated accumulation (sampling during a specific gate signal). The last three channels have a second accumulator for advanced digital filtering.

Each channel has its own result comparator, accumulator, and dedicated interrupt vectors for fast response to new data. The ADC’s control and data registers are on a fast peripheral bus, allowing quick CPU access. It is clocked from a dedicated generator, operating between 32 MHz and 320 MHz.

Compared to previous generations like the dsPIC33C, the dsPIC33A ADC offers more channels, higher speed, better accuracy, and greater flexibility.

ADC Key Features

• Up to 40 Msps conversion rate for each ADC core
• Multiple ADC cores depending on product family
• Up to 26 analog input pins
• Up to 20 conversion channels:
  • For any channel, any input signal pin (negative and positive) can be assigned
  • No dedicated core anymore
  • Any channel can have a different trigger source
  • Each channel can be set for a different sampling time
  • Each channel has a dedicated result comparator
  • Any channel supports several result accumulation modes
• Second Accumulator on the last three channels to implement a second-order filter

This diagram explains how the channel, when triggered, controls the analog positive and negative inputs, sampling time, and how the channel processes the result of the conversion.

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Peripheral Architecture

Clock

The ADC control and data Special Function Register (SFRs) are located on the fast peripheral bus, which equates to CPU R/W access to ADC registers in one instruction cycle.

To operate at maximum speed, the ADC must be clocked at 320 MHz. The clock signal for the ADC comes from the clock generator #6. Basic ADC clock generator #6 initialization code is shown:

Analog Signal Inputs

Each ADC channel can be assigned to any analog input. In addition to external analog input pins, the ADC has internal references from an 0.8V reference voltage (band-gap source), and a temperature sensor (diode). Each ADC channel supports true differential analog inputs. Up to four negative analog inputs are available.

Trigger Sources

• Each channel can have a trigger different from other channels
• Three trigger options are common for all implementations:
  • Software trigger
  • Back-to-back conversion trigger
  • Internal timer
• The ADC can be triggered from other device modules such as MCCP/SCCP, CLC, Pulse Width Modulation (PWM), external pin, and others

Modes of Operation

Each channel has the following operation modes:

• Single Conversion
• Integration (accumulation of any number of samples specified by a counter in SFR)
• Oversampling (accumulation of a fixed number of samples: 4, 16, 64 or 256)
• Gated Accumulation (samples accumulation until the gate signal is de-asserted)

Accumulator Overflow Mode

• Used for the filter implementation
• The last three channels have a second accumulator, allowing for a 2nd-order filter

Interrupts

Each channel has two dedicated interrupt events:

• ADC Result Ready Event
  • Single mode – one interrupt per conversion
  • Multiple Conversion (Accumulations) mode – one interrupt when all accumulations are finished
• Result Comparator Event

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Example Application

To run a conversion, a channel must be initialized, the ADC must be enabled, and the channel must be triggered. The code to do this is shown:

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