dsPIC33A Bidirectional Serial Synchronous (BiSS) Communication Peripheral

Overview

The dsPIC33A Bidirectional Serial Synchronous (BiSS) module is a new peripheral for high-speed, bidirectional, serial, and synchronous communication, commonly used in industrial automation and sensor applications. The BiSS module supports BiSS/BiSS-C and SSI protocols, operates up to 10 MHz, and is compatible with RS-485/RS-422 transceivers for robust, long-distance communication. 

Key features include support for one channel with up to four clients, 64-bit sensor data handling, variable clock rates, line delay compensation, and safety features like CRC, error, and warning flags. The module uses three serial lines and several I/O pins (all 3.3V, single-ended), which can be mapped flexibly using Peripheral Pin Select (PPS). 

The BiSS protocol operates in cycles, starting with synchronization, followed by data and control bit exchanges between host and client, and includes automatic line delay measurement and compensation. The module supports three main communication types: sensor/actuator (for real-time data), control (for register read/write), and command (for broadcast or addressed commands). 

Additional features include memory bank switching for efficient data handling, flexible CRC options for data integrity, and detailed error detection. Interrupts are provided for end-of-transmission and error events, allowing responsive and reliable system operation. 

Typical applications include interfacing with rotary and linear encoders, torque sensors, motor feedback systems, and CNC or robotics drives, making the dsPIC33A BiSS module ideal for precise, high-speed industrial control. 

Features

New dsPIC^® Digital Signal Controllers (DSCs) Peripheral

• Bidirectional data communication
  • Serial, synchronous, and continuous
• BiSS/BiSS-C and SSI compatibility
• Cyclic at high speeds
• Auto Get Sense Feature
• Variable clock rate
• Line delay compensation
• Safety features such as CRC, error flags, and warning flags
• Typical use with RS-485/-422 physical interfaces
• Types of host and client configurations
  • Host and single client (point-to-point)
  • Host and multiple clients (point-to-point)
  • Host and multiple clients on bus (bus configuration or BiSS)

Applications

The BiSS peripheral can be used in many applications that require communicating with the following types of sensors:

• Various encoders
  • Rotary, linear, magnetic, Hall, etc.
• Torque sensors
• Motor feedback
• Manufacturing robotics motor drives
• CNC drives

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Peripheral Architecture

High-Level Block Diagram

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Clocking Subsystem

• SFREQ = SCD Frequency
• Value = Number that the respective register is set to

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Communication Types

There are three types of communication:

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BiSS Protocol Format

• a: Active high on MA CLK and SLO line, then Acknowledge starts it off, and a start bit, Control Data Slave/Client (CDS)
• b: Followed by the position data, which is the Single Cycle Data (SCD) and then a timeout
• c: During the time-out on the SLO line there is a Control Data Master/Host (CDM) bit that is transmitted on the CLK line
• d: After time-out on SLO and CDM bit on MA, cycle restarts

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Control Frame

The control frame shows how multiple SCDs combine to form a CDM and CDS frame (control communication).

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Operating Modes Summary

• Control communication has two types of options, read and write, but this is only to the client’s registers.
• Command communication has two types of options, broadcast or addressed. They can read/write or do other various things, depending on the client’s definition of what the command does.

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Sensor/Actuator Communication

• Single GETSENSE – Discrete software triggered
• AUTOGETSENSE – Auto triggered based on AGS frequency

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Control Communication

Read Register

1. The host requests contents from the register address through the CDM frame.
2. The client responds with data through the CDS frame.

Write Register

1. The host sends the address, and then the data to be written into the client register through the CDM frame.
2. The client responds with data confirmation through the CDS frame.

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Command Communication

Broadcast Mode

The host sends 0 for IDS (held low) through the CDM frame, which signals a broadcast communication, and then the command is given.

Addressed Mode

1. The host sends the ID through the CDM frame, and then the command frame is given.
2. The client responds by acknowledging the ID through the CDS frame.

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Channel Initialization

The Channel Initialization (INIT) Sequence resets various status bits to initialize a communication channel. These bits include <SCDERR>, <REGERR>, <DLYERR>, <AGSERR>, <REGEND>. It also starts an automatic line delay calculation. Line delay is considered the time between the second rising edge of MA and the falling edge of SL.

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Line Delay Compensation

After the line delay measurement is taken during the initialization (INIT) sequence, the line delay value will be saved into <B1SCDATA0L> and automatic line delay compensation will occur. To calculate the line delay in seconds, the following equation can be used:

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Memory Bank Switching

Since the BiSS can operate at high transmission speeds, the BiSS module incorporates memory bank switching. The BiSS module has two memory banks: BANK0 and BANK1. This allows it to read and write to one memory bank while also receiving the next transmission. The bank switch occurs at the end of a BiSS Frame.

Bank switching is enabled and occurs by default, but can be disabled by setting the <B1CTRLCON.BANKSWEN>  This is the syntax we will be using to show which bit in a given register is to be referenced in the text of our training materials. (i.e. <registername.bitfieldname>)mouseover  bit, which disables use of BANK1. When bank switching is enabled, the <B1INSTR.BNKLOCK> bit can be used to inhibit or delay a bank switch, to allow safe access to the memory bank during critical read or write operations. Also, you can manually switch banks with the <B1INSTR.SWBANK> bit.

Monitoring capabilities are offered by these two bits:

• Any switch bank failure - <B1CHSTAT.BKSWERR>
• Number of the RAM Bank being read - <B1CON.BNKNUM>

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Cyclic Redundancy Check (CRC)

The BiSS peripheral contains a dedicated CRC generator to verify transmission integrity. The control and command frames can also include a CRC. The CRC (Data Channel or Control) being transmitted determines where these values will be transmitted in the protocol. The type of CRC also determines how many bits are available; up to 17 bits for Data Channel CRC and four bits for Control CRC. 

Settings for the CRC can be configured in the <B1CLTCONx> and <B1CTRLCONx> registers. The <B1CLTCONx.CRCSEL> bit (B1CLTCONx[15]) selects the purpose of the B1CLTCONx[14:8] bitfield. If CRCSELx = 0, then those bits are CRCLENx[6:0] and represent polynomial selection by length for the single-cycle data CRC Check. CRCSELx = 1 means those bits are called CRCPOLYx[6:0] and the polynomial for SCD CRC Check bits.

<B1CTRLCON.NOCRC> controls the storage of CRC in RAM. A value of zero means that CRC of SCD is stored in RAM, while a value of one means all client CRC of SCD is not stored in RAM.

Finally, B1CLTCON[31:16], <B1CLTCONx.CRCSEEDx[15:0]>, is where you set the polynomial CRC calculation start value or seed.

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Interrupts

The BiSS module generates two interrupts, End of Transmission (EOT) and Transmission Error (ERR). These interrupts can be used by clearing and enabling their appropriate interrupt flags.

End Of Transmission (EOT) Interrupt

The EOT interrupt is enabled using the relevant IECx register, and the flag is cleared and set in the appropriate IFSx register. This interrupt is asserted each time a successful transmission has completed.

This interrupt is useful if you want to read the SCD data immediately within the interrupt handler routine. 

Transmission Error (ERR) Interrupt

The ERR interrupt is enabled using the relevant IECx register, and the flag is cleared and set in the appropriate IFSx register. This interrupt is asserted when any of the BiSS error bits are set. These errors include:

• Transmission Error – <B1STAT.ERR>
• AGS Error – <B1STAT.AGSERR>
• Delay Error – <B1STAT.DLYERR>
• SCD Transmission Error – <B1STAT.SCDTXERR>
• Register Error – <B1STAT.REGERR>
• Bank Switch Error – <B1CHSTAT.BKSWERR>

This interrupt is useful for halting the operation immediately upon error. The user can then read the status flags to determine the specific error and take steps to resolve the problem. 

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Applications

The BiSS peripheral is used in the following communication applications:

• Various encoders
  • Rotary, linear, magnetic, Hall, etc.
• Torque sensors
• Motor feedback
• Manufacturing robotics motor drives
• CNC drives

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