dsPIC33A Configurable Logic Cell (CLC) Peripheral
Overview
This page covers the dsPIC33A Configurable Logic Cell (CLC), a flexible logic block for smart, connected, and secure embedded control. The CLC allows you to create custom logic functions inside the microcontroller without extra hardware.
Key features include support for up to 32 input sources (from external pins or other peripherals), combinational and sequential logic modes, edge detection, interrupt generation (even in Sleep mode), signal inversion, and the ability to route signals between otherwise unconnected peripherals. The CLC can also generate delays and chain outputs to other CLC modules for more complex logic.
The CLC architecture consists of input multiplexers, four data gates (each selecting from up to eight sources), a logic function block, and output routing. Both true and inverted forms of each input can be used. The output (LCOUT) can be sent to an I/O pin or other modules, and rising or falling edge interrupts can be enabled.
A typical application is Frequency Shift Keying (FSK) generation, where two CLC modules use UART data and different clock sources to modulate logic levels for communication. The dsPIC33A CLC is functionally the same as the dsPIC33C version.
Features
- General-purpose logic block
- 32 input sources, including external pins and other device peripheral outputs
- Combinational Logic modes
- Sequential Logic modes
- Edge detection and interrupt generation when the CPU is in Sleep
- Delay generation
- Inversion logic
- Signal routing between otherwise unconnected peripherals
The input data selection MUXes route input signals to the four data gates. Each of the four data gates can then select any of the 32 input signals to pass along to the logic functions. The output of the logic function is then supplied to the internal logic and external pin, and can generate interrupts. The output of a CLC module can also be routed to the input of another CLC module to create more complex logic functions.
High-Level Block Diagram
Peripheral Architecture
Source Multiplexers
Each logic cell in the CLC takes four inputs, one from each of the four data gates (Gate 1 shown). Each data gate is connected to eight input sources. The module has four input source multiplexers. Each of the four data selection multiplexers feeds one of the four logic function input gates.
Data Gates
Four logic input gates are used to route input sources from the data selection multiplexers into the four logic function inputs. The true and negated forms of each input source signal are available for use by each logic gate. There are up to eight signals that can be enabled for use by each logic function input. Any number of the eight signal sources may be enabled for each of the four logic function inputs.
Logic Functions
CLC Output
LCOUT is the logic cell output and is routed to the I/O port pin or to other modules within the device. In all cases, the signal value is taken after the LCPOL inverter. To observe this output on an I/O pin, you will need to set LCOE.
Interrupts
Two types of interrupts can be enabled:
- Rising edge interrupt events.
- Falling edge interrupt events.
Example Application
CLC Configuration for FSK Generation
Peripherals required for this application are:
- CLC1 and CLC2
- UART data as modulator signal
- Peripheral clock to modulate logic ‘1’
- LPRC to modulate logic ‘0’
