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dsPIC33A Analog Comparator With 12-bit PDM DAC Peripheral

Last modified by Microchip on 2025/10/14 15:54

Overview

Features

  • Pulse Density Modulation (PDM) Digital-to-Analog converter (DAC)
    • Each DAC is accompanied by one analog Comparator
    • dsPIC33A devices have multiple instances of DACs/CMPs (Comparators)
  • High-speed DAC for dynamic control reference
  • Main use is detecting voltage threshold crossing
    • Voltage or current in the control loop
    • Overcurrent/fault protection
  • Improved comparator response time (5 ns)
  • INL and DNL correction capability
  • Triggerable DAC data updates (from Pulse Width Modulation (PWM))
  • Transition mode disable for external DAC output use
  • 32-bit register interface

See the block diagram below. It shows multiple DACs sharing a common DACOUTx pin, and the comparator status is routed internally to other peripherals.

block diagram

High-Speed Analog Comparator with Slope Compensation DAC

Peripheral Architecture

Analog Comparator

  • Three rail-to-rail non-inverting inputs (CMPxA, CMPxB, CMPxC)
  • The inverting input is always the DAC output
  • Internal CMP out signals to other peripherals
    • PWM, CLC, PTG, xCCP
  • Pulse stretching – Glitch Filter, lengthens CMP output for CPU and peripherals
  • Digital filter – Noise filter, output must be stable for three samples
  • Configurable interrupt generation

Dedicated Pulse Density Modulation DAC Overview

  • 12-bit resolution
  • Multimode Multipole RC Output Filter
    • Different filter profiles
    • Automatic switching control
    • Dedicated timers for timing control of filter modes
  • Dedicated support for multiple modes/applications
    • Slope Generation
    • Hysteretic Control
    • Triangle Wave
  • Output buffer for external use

DAC Operation

  • The DAC consists of two stages
    • Pulse Density Modulation (PDM) unit
    • Digitally controlled multistage RC filter
  • The phase accumulator circuit generates an output stream of pulses
  • The density of the pulse stream is proportional to the input data value and the output voltage
  • Pulse stream is filtered with an RC filter to yield an analog voltage
  • The DAC output is connected to the negative input of the comparator
    • Output limited to 5% to 95% of full scale to guarantee performance specs
    • Values near limits are not prohibited, but incur excessive ripple

DAC Operating Modes

  • Standard – Set to static value as threshold
    • Each write will enable the transition mode filter
  • Dynamic modes
    • Slope: Supports slope compensation applications
    • Hysteretic: Current control method (LED driver)
    • Triangle: Audio applications

Slope Mode Overview

  • Supports peak current control with slope compensation
  • DAC generates sawtooth reference waveform iREF
    • PWM Duty Cycle (DC) is truncated on CMP trip
  • Synchronized to PWM
    • PWM provides start event
    • Optional stop event
  • Multiple output filter transitions
    • Controls ramp rate, waveform shape
    • Transition (fastest)
    • Fast
    • Slow (most accurate)

Slope mode

Slope Mode Features

  • Selectable start and stop triggers
    • Selectable PWM instance
      • One of two PWM Analog-to-Digital Converter (ADC) triggers
        •  Set by one of PWM’s TRIGy timers
    • Start event reset slope generator
    • Stop event restarts control cycle if no CMP trip
  • Programmable voltage range
    • Set by DACDAT and DACLOW
  • Ramp slope set by DAC Slope Data Register (SLPxDAT)
    • Bits of change per clock

Slope Mode Control Sequence

  1. Slope start from PWM
    1. Output filter to fast mode
  2. CMP trip
    1. PWM output truncated
    2. Output filter to transition mode
    3. Transition and steady state timers (TTR, TSS) started
  3. Transition timer expires
    1. Output filter to slow mode
  4. Steady state timer expires
    1. Output filter to fast mode

Slope mode control

Hysteretic Mode Overview and Features

  • Power control applications, including LED driver
    • Fast response from dedicated hardware
    • Variable frequency operation
  • Window comparator function using only one CMP
    • DACDAT and DACLOW are programmable limits
  • DAC and PWM work in conjunction to implement control loop
    • DAC to PWM on/off control signals available on PPS
    • Route to PWM’s PWM Control Input (PCI) to gate PWM output
    • PWM has no PER or DC, Fault override pin states are used
  • Dedicated blanking timer to prevent spurious trips
    • Automatically restarts on each transition
    • The filter is in transition mode with increased ripple

Hysteretic Control Sequence

  1. The output signal reaches the low limit
    1. CMP trips on the falling edge
    2. DAC sends a signal to the PWM to stop
    3. CMP reverses edge detect polarity
    4. Blanking counter re-started
  2. Output signal reaches high limit
    1. CMP trips on the rising edge
    2. DAC sends a signal to the PWM to start
    3. CMP reverses edge detect polarity
    4. Blanking counter restarted

Hysteretic control

Triangle Wave Mode

  • Enabled with Triangle Wave Mode Enable (TWME) bit in the DAC Slope x Control Register (DACxSLPCON)
    • Also requires SLOPEN bit set in DACxSLPCON
  • Voltage amplitude is set with DACxDATH and DACxDATL values
  • Period is set with SLPDAT
    • Counts per step @ 250 MHz
    • Data in 12.4 format (integer/fractional)

Triangle Wave

Example SLPDAT calculation:

  • Given:
    • Desired Period = 8 uS (4 uS each slope direction)
    • DAC clock = FIN/2= 250 MHz
    • Amplitude = 1 V to 2V
    • DACxDATL = 1241, DACxDATH = 2481
  • SLPDAT = (DACxDATH – DACxDATL) *16 / (TSLOPE/TDAC)
  • SLPDAT = 1240 * 16 / (4 uS/4 ns) = 20 = 0x14

The up or down ramp has 1000 DAC cycles to transition 1240 counts. Value of 0x14 in 12.4 format is 1.25 counts per step.

Data Updates From an External Trigger

  • DAC can control the timing of data updates
    • Update trigger is from the PWM module
    • DAC data updates can be synchronized to PWM events
  • DAC contains a buffer register in the high-speed clock domain
    • Update trigger is DAC’s Slope Start[4:1] signal
    • Can select PWM1 - PWM4’s ADC trigger 1
  • Enabled with the External Triggered Data Update (EXTUPD) bit in DACxCON

Transition Mode Disable

  • Disables automatic invocation of transition mode on data write
    • For using the DAC output as an external comparator reference
    • Prevents ripple induced by transition mode’s limited filtering (slows response time)
    • No comparator blanking feature is available for the external comparator
      • Comparator may falsely trip on the DAC output ripple due to the transition mode
  • Controlled by Update Transition Mode Disable (UPDTMDIS) bit in DACxCON register
  • UPDTMDIS only affects entry to transition mode due to data write
    • No effect on slope, triangle of hysteretic modes

Calibration and Hardware Compensation

INL Correction

Integral Nonlinearity (INL) correction flattens the INL curve using rise and fall time compensation (static correction).

  • DAC output stage drive strength is trimmed/compensated
    • Balances edge rise and fall times
    • Separate control for high and low drivers
  • Production test will calculate INLADJ trim values
    • Store in flash calibration area
    • Single value used across manufacturing lot
    • User code must copy calibration values to:
      • POSINLADJ[5:0] – Positive INL Correction value
      • NEGINLADJ[6:0] – Negative INL Correction value
  • You can also calibrate using ADC or another reference

DNL Correction

Differential Nonlinearity (DNL) correction mitigates spikes at bit boundaries (512, 1024..) with ripple reduction and idle tones (dynamic correction).

  • Falling-edge pulse stretching
    • Automatic control in hardware
    • Low driver strength is reduced as needed (slows fall time)
  • Enabled with Ripple Reduction Enable (RREN) bit in DACxCON register
  • You can further tune with DNL Adjustment Override bits (DNLADJ[4:0])
    • Shortens pulse stretching calculated in hardware

Configuration

Basic Module Setup

  1. Select one of the three analog inputs
  2. Make sure the corresponding Analog Select bit (ANSEL) bit is set to configure the DACOUTx pin for analog operation
  3. Configure DAC to reference voltage
  4. Configure the comparator (CMP) for the appropriate application
  5. Enable DAC/CMP
Information

Note: When using the DACOUTx pin for the DAC, other pin functions can not be used. Also, a floating comparator (CMP) input will cause the output to chatter/ring.

Basic Comparator initialization

  1. Initialize DAC to set the reference point on the inverting input
  2. Input selection (INSEL)
  3. Output polarity (CMPPOL)
  4. Hysteresis level (HYSSEL)
  5. Digital filter if needed (FLTREN)
  6. Configure and enable interrupts if needed
  7. Enable DAC/CMP module (DACON = 1)

Basic DAC initialization

  1. Initialize DAC input clock (CLKGEN 7, 500 MHz)
  2. Write data value to DACDAT (see note below)
  3. If external output is needed, set output enable DACOEN
  4. Enable DACx module with DACEN = 1
  5. Enable All Comparator (DAC/CMP) modules (DACON = 1)
Information

VDAC = DACDAT x (VDD)/4095, where 0X0CD <= DACDAT <= 0XF32 (output range of 5% to 95% of AVDD)

DAC Clocking Subsystem

  • DAC is on ½ speed peripheral bus
    • Special Function Registers (SFRs) operate and update at half the CPU rate
  • The DAC high-speed clock is supplied by CLKGEN 7
    • Asynchronous to CPU/DAC registers
    • Must configure CLKGEN 7
    • Output filter configured for 500 MHz operation
  • Clock selection register bits are no longer available

Interrupts

One interrupt signal from each DAC/CMP module

  • Interrupt event is comparator trip (CMPx)
  • No interrupts from DAC

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Example Application

Slope Compensation in Buck Converter With Peak Current-Mode Control

  • Regulates output voltage
    • ADC measures output voltage
    • SW adjusts DACDAT as needed (current limit)
  • CMP truncates PWM duty cycle
    • DC is set to a value larger than max on time
  • Current Limit PCI gates PWM
    • Used dedicated CL pin state data
    • Latched to the end of the PWM cycle

Slope Compensation in Buck converter

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