dsPIC33A I2C Peripheral
Overview
This page covers the dsPIC33A I2C (Inter-Integrated Circuit) module, its main features, and how it works. The I2C module allows the microcontroller to communicate with other devices using the I2C protocol, supporting both Host and Client modes at standard speeds (100 kHz, 400 kHz, 1 MHz) and 7- or 10-bit addressing. It includes features such as automatic clock stretching, multi-host support, SMBus and Intelligent Platform Management Interface (IPMI) compatibility, and advanced error checking.
You will learn how the module manages start and stop conditions, data transfer, acknowledgments, and collision detection. The I2C bus uses two open-drain lines (SDA and SCL) with pull-up resistors. In Host mode, the microcontroller controls the bus and can handle arbitration and timing. In Client mode, it responds to addresses and can support strict protocols.
New features include Smart mode for easier automation, frame and packet error detection, and several timeout options for reliable operation. The module also supports multiple interrupts for data transfer and error handling.
A typical example is reading data from an EEPROM, where the host sends commands and reads data back from the client. By the end, you will understand how to use the dsPIC33A I2C module for robust and efficient device communication.
Features
- Independent host and client logic
- Supports 100 kHz, 400 kHz and 1MHz bus specifications
- 7-bit and 10-bit device addresses
- Automatic clock stretching
- Multi-host support
- Supports data hold time for SMBus (300 ns or 150 ns) in Client mode
- Supports SMBus v2.0 and v3.0 input voltage levels
- Supports the IPMI standard
The I2C module consists of:
- Baud rate generator
- Control logic for:
- Start/stop generation
- Start/stop detection
- ACK/NACK generation
- Collision detection
- Clock stretching
- Address match detection
Peripheral Architecture
Host Mode
- Host drives SCL and controls the bus
- Configurable for 100 kHz, 400 kHz and 1 MHz bus speeds
- SCL high/low can be configured independently using I2CxBRGH/I2CxBRGL
- Bus Idle timer can be configured to check if the bus is free to initiate the start condition
- Bus arbitration, clock synchronization, and bus collision to support multi-host operation
The wired-AND nature of the SDAx line permits arbitration. Arbitration takes place when the first host outputs ‘1’ on SDAx by letting the SDAx float high, and simultaneously, the second Host outputs ‘0’ on SDAx by pulling SDAx low. The SDAx signal will go low. In this case, the second host has won bus arbitration. The first host has lost bus arbitration and thus has a bus collision.
The clock synchronization occurs when the host deasserts the SCLx pin (SCLx intended to float high). When the SCLx pin is released, the BRG is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the BRG is reloaded with the contents of I2CxHBRG[23:0] and I2CxLBRG[23:0] begin counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device.
Client Mode
- Client responds to the host; it cannot initiate the communication
- Configurable for 7-bit or 10-bit addresses
- Client mode can be configured for:
- Two unique addresses
- Range of address
- General call address
- Address bit masking
- Strict mode to support IPMI
Smart Mode (New Feature)
In Client mode, hardware will release the clock (SCLREL) based on the suspend state of the bus (SSPND bit). In Host mode, hardware will automatically enable reception (RCEN=1) to continue reading. Smart mode, along with DMA, can be used to reduce CPU interaction. To further reduce CPU interaction, Acknowledge control (ACKC) can be used to automatically ACK/NACK.
Frame Error (New Feature)
A Frame error will be detected when the START or STOP condition interrupts transmission or reception.
- Frame error due to STOP condition: receiver returns to Idle state and waits for START condition.
- Frame error due to START condition: Client considers it as a new start condition, and it moves to the address receive phase.
Packet Error Checking (PEC) (New Feature)
The Packet Error Checking (PEC) mechanism improves reliability and communication robustness. It uses a CRC-8 calculator for all the message bytes, including addresses and read/write bits. It can not be used on ACK/NACK bits, START/STOP or REPEATEDSTART conditions. PEC can be configured to append/do not append.
Bus Timeout (New Feature)
| SCL Low Timeout (tTIMEOUT) | SCL low timeout (tTIMEOUT) allows a host or client to conclude that a defective device is holding the clock low indefinitely or a Host is intentionally trying to drive devices off the bus |
| Bus IDLE Timeout (TBUF) | Bus Idle timer can be used to define bus free time (TBUF) between Stop and Start |
| Client Extended Timeout (tLOW:SEXT) | Client extended timeout allows a host or client to extend its clock cycles measured from the initial START to the STOP |
| Host Extended Timeout (tLOW:MEXT) | Host extended timeout is used for clock extension within one byte in a message as measured from, START to ACK, ACK to ACK, or ACK to STOP. |
Interrupts
The I2C peripheral has four interrupts:
- Receive Buffer Full Interrupt (Trigger to DMA)
- Transmit Buffer Empty Interrupt (Trigger to DMA)
- Generic Module Interrupt
- Bus Idle time out
- End Of Packet
- Error Interrupt
- Client Interrupt
- Host Interrupt
- Error Interrupt
- Bus Collision Error
- Bus SCL low time-out error
- Host Cumulative time-out error
- Client Cumulative time-out error
- Frame Error
- CRC error
- NACK error
Different interrupts can be enabled/disabled using the Interrupt control register (I2CxINTC).
Example Application
I2C Bus Protocol
| Condition | Description |
|---|---|
| Start Data Transfer (S) | After a Bus Idle state, a high-to-low transition of the SDAx line while the clock (SCLx) is high determines a Start condition. |
| Stop Data Transfer (P) | A low-to-high transition of the SDAx line while the clock (SCLx) is high determines a Stop condition. |
| Repeated Start (R) | After a Wait state, a high-to-low transition of the SDAx line while the clock (SCLx) is high determines a Repeated Start condition. Repeated Starts allow a host to change bus direction or address a client device without relinquishing control of the bus. |
| Data Valid (D) | After a Start condition, the state of the SDAx line represents valid data when the SDAx line is stable for the duration of the high period of the clock signal. There is one bit of data per SCLx clock. |
| Acknowledge (A) or Not Acknowledge (N) | All data byte transmissions must be Acknowledged (ACK) or Not Acknowledged (NACK) by the receiver. The receiver will pull the SDAx line low for an ACK or release the SDAx line for a NACK. The Acknowledge is a 1-bit period using one SCLx clock. |
| Wait/Data Invalid (Q) | The data on the line must be changed during the low period of the clock signal. The devices may also stretch the clock low time by asserting a low on the SCLx line, causing a Wait on the bus. |
| Bus Idle (I) | Both data and clock lines remain high after a Stop condition and before a Start condition. |
I2C Message Protocol
I2C operates in one of the following modes:
- Host-Transmitter and Client-Receiver
- Client-Transmitter and Host-Receiver
The host sends a write address to the client, followed by one data byte (Host Transmit and Client Receive).
The host sends repeated start followed by read address to the client.
Client responds to host by sending a data byte (Client Transmit and Host Receive).
I2C Hardware Setup
- SDAx and SCLx lines are bidirectional
- SDAx and SCLx lines are open-drain to perform the wired-AND function of the bus
- External pull-up resistors are used to ensure a high level when no device is pulling the line down
dsPIC33A Reads Data From EEPROM
This example shows how the dsPIC33A (host) uses its I2C peripheral to read data from an EEPROM (client):
- The host sends the start condition followed by the EEPROM address with R/W=0.
- Once the EEPROM acknowledges its address, the host sends the address/location from which it wants to read the data.
- The host sends repeated start conditions followed by the EEPROM address with R/W=1 to change bus direction.
- The EEPROM responds by sending back the data in the memory location.