dsPIC33A I/O Ports Peripheral

Overview

On this page, you will learn about the dsPIC33A’s I/O ports and related features. The microcontroller gives you flexible control over each pin using registers like TRISx for direction (input or output), LATx for setting output values, and PORTx for reading pin states. You can also enable open-drain outputs, use internal pull-up or pull-down resistors, and detect changes on input pins to trigger interrupts. 

The dsPIC33A supports Peripheral Pin Select (PPS), which lets you map digital peripheral functions to almost any remappable pin. This makes it easy to assign functions like UART or interrupts to the pins that best fit your design.

A special feature called the IO Integrity Monitor (IOIM) helps ensure functional safety. It checks that signals sent out from the microcontroller are correctly received, either internally or at an external point. The IOIM can detect mismatches, compensate for signal delays, and even simulate faults for testing. If a mismatch is found, it triggers an interrupt so your software can respond. 

You will also learn that different I/O registers operate at different speeds, depending on the peripheral bus clock. Some registers are fast, while others are slower, which can affect how quickly you can read or write to them. The IOIM can use either an internal or external clock source. 

This page provides an overview of the dsPIC33A IO Port. For more details, please refer to the "dsPIC33AK512MPS512 Family Data Sheet".

Features and Register Set

• GPIO Data
  • PORTx, LATx
• GPIO Analog Select
  • ANSELx
• GPIO Direction Control
  • TRISx
• GPIO Open-Drain Control
  • ODCx
• Pull-up Control
  • CNPUx
• Pull-down Control
  • CNPDx
• Change Notice
  • CNEN0/1x, CNSTATx, CNFx
    • Detects positive or negative edge events
• Peripheral Pin Select (PPS)
  • RPORx, RPINRx
    • Flexible remapping of peripheral pins
• IO Integrity Monitor (IOIM)
  • IOIMxCON
    • New module for safety applications

Peripheral Architecture

Input/Output Circuits

A general purpose I/O port that shares a pin with a peripheral is generally subservient to the peripheral. Once enabled, the peripheral selects whether the peripheral or the associated port has ownership of the I/O pin.

A MUX and its associated logic controls interaction between peripherals and port logic. When a peripheral is enabled but the peripheral is not actively driving a pin, the port is still allowed to drive the pin. This is useful for loop through, in which a port’s digital output drives the input of a peripheral that shares the same pin.

When a peripheral is enabled and the peripheral is actively driving an associated pin, the IO MUX disables the use of the pin as a general purpose output. The I/O pin value may be read by the port, but the LATx[n] output value for the port is ignored.

The output and input circuits of the I/O are independent. The block diagrams of the output and input I/O circuits are shown in Figure 1 and Figure 2.

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Peripheral Pin Select (PPS)

The PPS feature allows remapping of pin and port functions and can be configured to best suit an application. This simplifies board design and allows peripherals to be connected to one another with or without a pin.

Remappable Input Functions

Figure 3 shows the structure of a remappable input. The control logic is based on the peripheral input function, through selection of which remappable Pin (RPn) is used as the input source. Each peripheral input function (for example, U1RX) is associated with a register bit field (U1RXR) to select which RPn pin to connect with. More than one peripheral can select the same input pin.

For example, to assign pin RP1 to the U1RX input function, the following code is executed: _U1RXR = 1;.

• U1RXR is the input function register
• 1 is the RP pin number identifier

Remappable Output Functions

Figure 4 shows the structure of a remappable output. Unlike the inputs, the control logic is based on the remappable pin. Each RPn pin (for example, RP2) has an associated register bit field (RP2R) to select which peripheral output function is routed to the pin. The output of one peripheral can be mapped to multiple RPn pins.

For example, to assign the U1TX output function to pin RP2, the following code is executed: _RP2R = 9;.

• RP2R is the RP pin number register
• 9 is the output function identifier (=U1TX - see device data sheet for defined output function identifiers)

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I/O Integrity Monitor (IOIM)

The port module includes integrity monitoring circuity, as shown in Figure 5, to validate I/O functionality in critical applications by comparing a device output signal against a reference signal. If a mismatch is detected, an event is generated to allow software to take action as needed for the application. A programmable blanking timer is included to account for the feedback path delay. The timer is reset on a change of state in the reference signal. A counter is included to keep track of the number of mismatch events.

Typical uses include:

• To increase protection for customers who are building safety-sensitive applications
• To simplify structural tests for safety applications
• To ensure the pin has been connected correctly in its final environment by using structural tests

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Clocking Subsystem

dsPIC33A implements a 16 kB Special Function Register (SFR) space which is accessed through a split peripheral bus running at several speeds. The various IO Port registers are accessed at the speeds shown in Table 1:

Interrupt Generation

Change Notification

GPIO pins are able to assert an interrupt when an input level on a pin changes, based on the configuration of CNCONx.CNSTYLE, CNEN0x, and CNEN1x registers per Table 2.

IOIM Mismatch Error

The IOIM is able to assert an interrupt for every mismatch between signals on the reference and feedback pins. It can also assert an interrupt when the CHECON.FLTINJ bit is set during Artificial Test mode.

IOIM1IF and IOIMxSTAT.ERR are set when an interrupt is asseerted.

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