dsPIC33A SPI Peripheral

Overview

This page covers the dsPIC33A Serial Peripheral Interface (SPI) module, which provides flexible serial communication in both Host and Client modes. The module supports both standard and enhanced buffer modes, with configurable data widths ranging from 2- to 32-bits (including 8-, 16-, and 32-bit transfers). It features separate shift registers and FIFOs for transmitting and receiving data, and allows programmable interrupt events for different data sizes.

In Host mode, the module initiates communication, controls the Chip Select (CS) line, and manages data transfer using the MOSI and MISO lines synchronized by the SPI clock. In Client mode, the device waits for the host to start communication by pulling CS low. The module also supports Framed SPI mode, where a frame synchronization pulse is used, and Audio SPI mode, which adds support for audio protocols with dedicated bit and left/right clocks.

The SPI module offers three groups of interrupts: receive interrupts (for buffer and overflow events), transmit interrupts (for buffer and overflow events), and general interrupts (for frame errors, busy status, and underruns). These can be managed through the SPI status register. Overall, the dsPIC33A SPI module is a versatile solution for high-speed, reliable serial data exchange in embedded systems.

The SPI peripheral includes:

• Host and Client modes support
• Standard and Enhanced Buffer modes
• User-configurable 8-bit, 16-bit, and 32-bit data width
• Two separate shift registers for transmission and reception
• Two separate FIFOs for transmission and reception
• User-configurable variable data width, from 2- to 32-bit
• Programmable interrupt event on every 8-bit, 16-bit, and 32-bit data transfer
• Audio Protocol Interface mode
• Framed SPI protocol support

Peripheral Architecture

Host Mode

• Decides when to trigger communication
• Selects the client by pulling the CS line low
• Data can be thought of as taking a direct path between the Most Significant bit (MSb) of one module’s shift register and the Least Significant bit (LSb) of the other, and then moving them into the appropriate transmit or receive buffer
• The data is sent out serially on the MOSI channel, using a shift register, and every bit is synchronized using the SPI clock generator
  • While every bit is shifted out, new data is received on the MISO channel from the client and is shifted in a receiver buffer

Client Mode

• Clients do not initiate any action and only act when the host initiates
• A client must always be available and must wait until the host pulls low its CS channel to start transmission from client to host

Framed SPI Mode

• Frame Host controls the generation of the Frame Synchronization pulse
• The SPI clock is generated by the SPI Host and is continuously running
• SPI Frame Modes can be grouped based on who generates the Clock and Sync Pulse
• Framed SPI mode requires the use of all four pins (i.e., using the SSx pin is not optional)

The FRMEN control bit (SPIxCON1[23]) enables Framed SPI mode and causes the SSx pin to be used as a Frame Synchronization pulse input or output pin. The FRMSYNC control bit (SPIxCON1[22]) determines whether the SSx pin is an input or an output (i.e., whether the module receives or generates the Frame Synchronization pulse). The FRMPOL control bit (SPIxCON1[21]) determines the Frame Synchronization pulse polarity for a single SPI clock cycle. The FRMSYPW control bit (SPIxCON1[19]) can be set to configure the width of the Frame Synchronization pulse to one character wide.

Audio SPI Mode

The SPI module can function in Audio Protocol Host and Audio Protocol Client modes. In Host mode, the module generates both the BCLK on the SCKx pin and the LRCK on the SSx pin. The SPI clock is generated by the SPI Host and is continuously running.

The SPI module provides support to the audio protocol functionality through four standard I/O pins. The four pins that make up the audio protocol interface modes are:

• SDIx: Serial Data Input for receiving sample Digital Audio Data (ADCDAT)
• SDOx: Serial Data Output for transmitting Digital Audio Data (DACDAT)
• SCKx: Serial Clock, also known as the Bit Clock (BCLK)
• SSx: Left/Right Channel Clock (LRCK)

BCLK provides the clock required to drive the data out or into the module, while LRCK provides the synchronization of the frame based on the protocol mode selected.

Interrupts

There are three types of interrupts. They can be enabled/disabled using the SPI status register (SPIxSTAT).

• Receive Interrupts
• Transmit Interrupts
• General Interrupts

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Application Example

The SPI bus is a synchronous serial communication interface based on four types of logic signals:

• SCK: Serial Clock (output from the host)
• MOSI: Host Output Client Input (data output from the host)
• MISO: Host Input Client Output (data output from the client)
• SS: Client Select (active-low, data output from the host)

Example Host-Client Communication

Example EEPROM Read

This is example shows an SPI host reading data from Electrically Erasable Programmable Read-Only Memory (EEPROM).

1. The host pulls the CS line to select the EEPROM start condition, followed by EEPROM address with R/W=0 .
2. The 8-bit read instruction is transmitted to the EEPROM, followed by a 16-bit address/location from which it wants to read the data.
3. The data stored in the memory at the selected address is shifted IN on the MISO pin.
4. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out in the EEPROM.
5. The read operation is terminated by raising the CS pin.

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