dsPIC33A UART Peripheral

Overview

This page covers the dsPIC33A Multiprotocol UART Module, a flexible serial communication interface for connecting PIC^® microcontrollers (MCUs) to computers, peripherals, and other devices. The UART supports both full- and half-duplex operation, with 8-deep transmit and receive First-In, First-Outs (FIFOs), 8-bit data width, configurable stop bits, and flow control options (XON/OFF and hardware). 

Key features include auto-baud calibration, error detection (parity, framing, buffer overrun), address detection, break transmission, and polarity control. The UART can operate in sleep mode and wake on sync break, and supports protocols like Digital Multiplex (DMX), IrDA^® standard, LIN/J2602, and Smart Card (ISO 7816). The dsPIC33A version uses 32-bit registers and adds a Write In Progress (WIP) bit for safer register updates. 

A UART character frame consists of a start bit, eight data bits, optional parity/address bit, and one or more stop bits. The module supports legacy and fractional baud rate modes, and can automatically synchronize to a transmitter’s baud rate. Address detect allows filtering of messages for multi-drop networks, and parity provides single-bit error detection. Flow control prevents data loss between devices. 

The UART module generates interrupts for buffer status, address matches, auto-baud completion, break reception, wake events, and various errors. Applications include standard serial communication, DMX lighting control, IrDA wireless data transfer, automotive LIN networks, and secure smart card transactions. 

Features

• The Universal Asynchronous Receiver Transmitter (UART) is a flexible serial communication peripheral used to interface PIC MCUs with other equipment, including computers and peripherals
• The UART is a full-duplex, asynchronous communication channel that can be used to implement protocols, such as RS-232 and RS-485
• Also supports the following hardware/protocol extensions:
  • DMX – Lighting control in entertainment and architecture
  • IrDA – Wireless data transfer
  • LIN/J2602 – Automotive control systems
  • Smart card (ISO 7816) – Secure transactions and access control
• Full or half-duplex operation
• Up to 8-deep TX and RX FIFO buffers
• 8-bit data width
• Configurable stop bit length
• Flow control
• Auto-baud calibration
• Parity, framing, and buffer overrun error detection
• Address detect
• Break transmission
• Transmit and receive polarity control
• Operation in Sleep mode
• Wake from Sleep on Sync Break Received Interrupt

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Differences from dsPIC33C

There is no major change with the module except for combining the 16-bit registers into 32 bits.

• Similar to other modules, UART is equipped with a dedicated clock generator in addition to the default UPB clock.
• Write in Progress (WIP) bit is added to UxPA and UxPB registers to indicate when these parameter registers can be updated.

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Peripheral Architecture

UART Block Diagram

• The Baud Rate Generator sets the transmission speed by generating clock pulses. It determines the rate at which data bits are sent or received over the UART interface, with a higher baud rate indicating faster communication.
• The Special Function Registers (SFRs) configure the various modes for the UART, establish different interrupt triggers, define specific communication protocols, etc. 
• The Interrupt Generator manages and generates UART-related interrupts (transmit, receive, error, and event).
• The Error and Event Detection block monitors data for errors (such as parity, framing, and overflow and special events (such as auto-baud event, wake event, etc.).
• The transmit buffer stores data to be sent from the MCU to an external device, allowing for efficient data transmission
• The receive buffer holds incoming data from the external device, enabling the MCU to retrieve and process it as needed.
• The Hardware Flow Control block controls the data flow between the MCU and an external device. It uses control signals, such as Request to Send (RTS), Clear to Send (CTS), Data Set Ready (DSR), and Data Terminal Ready (DTR), to regulate the transmission of data, preventing data overflow and ensuring reliable communication.

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UART Character Frame

UART character frame components:

• Start bit
• Eight data bits (D0-D7)
• Optional Parity/Address detect bit
• Stop bit (one or more, depending on the configuration) 

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Operation

Clocking and Baud Rate Configuration

This figure outlines the general clock system of the UART module.

• The CLKSEL[1:0] bitfield is used to configure the selection of one of the available clock sources for the UART.
• Depending on the BRGS bit, the frequency of the chosen clock source is divided either by 16 or four.
• The BRG[19:0] bitfield is then used to apply additional division to arrive at the final baud clock frequency.

There are two modes for generating the baud clock, Legacy and Fractional. The CLKMOD bit (UxCON[27]) controls this selection. When CLKMOD = 0, the BRG is in Legacy mode, and when it is 1, it is in Fractional mode.

In Legacy mode, the incoming clock is divided by 16 or 4 BRGS bit (UxCON[7]).

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UART Modes

This UART has a variety of modes that allow it to support many applications. The desired modes are selected by setting the appropriate value in the MODE[3:0] bitfield of the UART Configuration Register (UxCON[3.0]). There are the several versions of the standard Asynchronous mode (7-bit, 8-bit, 8-bit with parity, 9-bit with address detect), as well as modes to support DMX, IrDA, LIN, and Smart card protocols.

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Asynchronous Mode: Transmission

The critical component of the transmitter is the UARTx Transmit Shift Register (UxTSR). The shift register receives its data from the transmit FIFO buffer, UxTXB, which is loaded with data via software.

Transmission can be initiated by setting the TXEN enable bit, given that the UART module is powered on (ON=1). However, the actual transmission will not commence until the UxTXB register has been populated with data and the Baud Rate Generator (UxBRG) has generated a shift clock. Typically, during the initial transmission, the UxTSR register is empty. Therefore, when the TXEN bit is set, a transfer to the UxTXB register results in an immediate transfer to UxTSR.

A TX interrupt will be generated according to the TXWM[2:0] bits’ interrupt watermark setting. The TXWM bits can be configured to generate a TX interrupt when the buffer has one to eight empty slots.

The UARTx Transmit Buffer (UxTXB) has two associated flags to indicate its contents. The TX Buffer Empty Status bit, TXBE (UxSTAT[21]), indicates that the buffer is empty, and the TX Buffer Full Status bit, TXBF (UxSTAT[20]), indicates that there are no empty slots in the buffer, and it should not be written.

Set up asynchronous transmission:

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Asynchronous Mode: Reception

The critical component of the receiver is the UARTx Receive (Serial) Shift Register (UxRSR). Data is received on the UxRX pin. After sampling the UxRX pin for the Stop bit, any received data in the UxRSR register is transferred to the receive FIFO if it is empty. You can access and read the data stored in the RX FIFO through the UxRXB register.

Reception is enabled by setting the RXEN bit, provided that the UART module is turned on (ON=1). Clearing the RXEN bit will halt the receive shifter. As a consequence, RXIDL (UxSTAT[19]) is set to ‘1’.

An RX interrupt will be generated when a byte is received, according to the UART Receive Interrupt Select bits setting, RXWM[2:0] (UxSTAT[26:24]). The RXWMx bits can be configured to generate an RX interrupt when the RX buffer contains one to eight bytes.

When the RX interrupt is generated, relative to the Stop bit, is configurable using the STPMD bit (UxSTAT[22]). By default, an RX interrupt is generated in the middle of the Stop bit. Writing a 1 will move the RX interrupt to the end of the Stop bit.

Set up asynchronous reception:

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Auto-Baud Feature

The auto-baud feature allows the receiver to determine the baud rate of the transmitter and synchronize to it. The transmitter sends a byte value of 0x55 (Sync byte) to the receiver, and the receiver calculates the average bit time from the falling edges. The UxBRG register is then written with the corresponding value. The Sync byte (0x55) will not be stored in the Rx buffer. Auto-baud is supported in both Legacy and Fractional Baud Rate Generation modes (CLKMOD = 1 or 0). The Sync byte may be preceded by a Break.

To enable auto-baud, the ABDEN bit (UxCON[6]) is set, and the UART will begin to look for a falling edge (Start bit of Sync byte). While the auto-baud sequence is in progress, the UART state machine is held in Idle mode. On the fifth RX pin falling edge, an accumulated BRG counter value totaling the proper BRG period is transferred to the UxBRG register. Once the auto-baud process
is complete, the ABDEN bit will be cleared by hardware, and the ABDIF flag (UxUIR[6]) is set. If the ABDIE (UxUIR[2]) interrupt enable bit is set, an event interrupt will be generated. See the following figure for the Auto-Baud Detection sequence. 

If the fifth and final falling edge is not detected before the BRG counter rolls over, the ABDOVIF flag (UxSTAT[5]) will be set to indicate the condition. The flag cannot be cleared until ABDEN is cleared. If the ABDOVIE bit (UxSTAT[13]) is set, an error interrupt will be generated.

Set up auto-baud:

Alternatively, if a Break precedes the Sync and it is desired to detect the Break, use the following sequence:

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Other Features

Address Detect

• Used when multiple receivers are connected to a transmitter
• Allows a receiver to determine if the message is intended for it and to ignore those that are not
• If the 9th data bit is a ‘1’, the data is recognized as an address to be processed by the receiver
• An address mask is provided to allow multiple receivers to accept the same address

Parity Support

• Parity is a simple method of single-bit error detection
• Even parity is defined as an odd number of data bits whose values are ‘1’
• Odd parity is defined as an even number of data bits whose values are ‘1’

Break Character

• A Break character is defined as several consecutive low bit times, usually longer than a whole byte
• In Asynchronous mode, the UART will transmit a 13-bit long duration Break, and in receive, will flag 11 Low bit times as a Break sequence

Flow Control

• Flow control is used to prevent data loss between two devices
• One device may be slower or have to process data
  • Flow control allows a device to tell the other to wait before sending additional bytes that may overrun its buffers
• The UART supports two types of flow control:
• XON/OFF Messaging
• Hardware Flow Control

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Interrupts

Comprehensive List of UART Interrupts

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Applications

• Asynchronous mode
  • Legacy Serial Communication: Used to connect a microcontroller with FPGA/sensor/computer etc.
• DMX protocol
  • Lighting Control in Entertainment and Architecture: Essential for controlling lighting fixtures in concerts, theaters, architectural lighting, and more, allowing precise control of colors and effects
• IrDA protocol
  • Wireless Data Transfer: Utilized in early wireless data transfer applications such as infrared communication between devices like laptops, printers, and cell phones
• LIN protocol
  • Automotive Control Systems: Enables reliable and cost-effective communication between ECUs in vehicles, controlling power windows, central locking systems, lighting etc.
• Smart Card Protocol (ISO 7816)
  • Secure Transactions and Access Control: Used in various sectors for secure identification, access control, payment systems, and authentication, such as EMV cards in banking

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