dsPIC33A Watchdog Timer (WDT) Peripheral
Overview
On this page, you will learn about the Watchdog Timer (WDT) in dsPIC33A devices and how it helps keep your application safe and reliable.
The WDT monitors your software and can reset the device or trigger a trap if your program stops working properly. dsPIC33A has two WDTs, one for normal Run mode and one for Sleep/Idle mode. Each has its own timer and settings, so you can choose timeout periods from less than a microsecond up to 24 days.
You will learn that the WDT can be set up to either reset the device or just trigger a trap, and you can easily reset the WDT counter with the CLRWDT instruction. In Sleep/Idle mode, the WDT can wake up the device and run a special interrupt routine if needed.
The WDT is useful for low-power applications, letting the device sleep and wake up at regular intervals to perform tasks. You will also learn how to configure the WDT and use it to make your application more robust.
By the end of this course, you will know how to use the WDT in dsPIC33A devices to monitor your software and manage power efficiently.
Features
- WDT is designed to enable users to:
- Monitor the health of their application software
- Wake the device from Sleep/Idle modes
- Key features of WDT include:
- Two independent WDTs for Run mode and Sleep/Idle mode
- Distinct 5-bit postscalers for Run and Sleep mode counters
- Free-running timers with 32 configurable postscalers for each WDT
- Permits timeout values ranging from 640 ns to 24 days
- Generates a trap or reset to the processor in the event of a software malfunction
dsPIC33C to dsPIC33A comparison
- Improved WDT software control
- All bits of WDTCON SFR are now read and write.
- Therefore, writes to all bits of the WDTCON registers (except WDTCON.ON) are disabled once the module is enabled.
- WDT event control
- Resets due to WDT event can be controlled via the WDTRSTEN bit in the FWDT config fuse.
- WDT can be made to generate a device reset or a generic trap on a run mode event.
- Interrupt on Sleep/Idle WDT event
- WDT PWRSAV event Interrupt routine can be defined, to perform any desired task soon after waking up from Sleep/Idle mode.
- CLRWDT instruction to reset WDT
- WDTKEY sequence used in dsPIC33C is now replaced by the CLRWDT instruction.
- Hence, the control of resetting the WDT-counter is now held by the CLRWDT instruction alone.
- WDT during NVM operation
- WDT counter stall during NVM operation can be controlled through FWDT Config fuse.
- Depending on the application's criticality, this functionality can be used to prevent WDT from stalling during NVM operation.
Peripheral Architecture
WDT Block Diagram
The WDT has two separate counters, the run mode counter and the Power-Saving mode counter. When the device goes into a Power-Saving state (Sleep or Idle), the run mode counter is halted, the count is saved, and the Power-Saving counter starts. When the device wakes from sleep or idle, the run mode counter resumes counting, and the Power-Saving mode counter is held in reset.
Dual Watchdog Timer
Run-mode WDT
- Operates in normal Run mode
- Interrupts/resets the device
- Clocked from user selectable clock source
Sleep/Idle mode WDT
- Operates in PWRSAV mode
- Wakes up the device from PWRSAV
- Clocked from LPRC
Configuring the Watchdog Timer
The WDT is both a hardware and software-controlled module. Its configuration is controlled by software through the WDTCON register. However, it can also be controlled by hardware because the reset value of each bit in the WDTCON SFR is determined by the FWDT configuration (fuse) register. This allows the WDT to be preconfigured and enabled/disabled at device start-up.
Before enabling the WDT, the appropriate post-scalers, WDT Run mode clock source, and Window mode must be selected. When configuring the module in software, set these values first and then set the ON bit. If using the configuration fuses to enable the WDT on Power-On Reset (POR), the other settings must also be chosen and set correctly in the FWDT to ensure proper operation of the WDT.
The WDT is enabled or disabled by the WDT ON(WDTCON[15]) bit. When the ON bit is set, the WDT is enabled and writes to the WINSIZE [1:0], RMPS [4:0], RMCLK [1:0], SMPS [4:0], and WINDIS are disabled. Additionally, writes to the WDTCON register can also be locked using PACCON2[WDWTCONWR] to avoid accidental WDT writes. If the ON bit is cleared in the WDTCON register, the WDT is disabled and reset, and WDTCON SFR modification is allowed.
Run Mode WDT
When the WDT times out in Run mode, a device Reset/NMI is generated. Firmware can determine if the cause of the Reset was the WDT time-out in Run mode by testing the WDTO bit in RCON.
The WDT can be controlled to raise a device Reset or WDT generic trap on WDT time-out by modifying the WDTRSTEN bitย (FWDT[16]) in the FWDT configuration register.
For the equation in the diagram above:
- ๐๐ ๐๐ท๐ ->ย Run mode WDT Time-out
- ๐๐๐ถ๐ฟ๐พ -> Run mode WDT clock period
- ๐ ๐๐๐ -> Run mode WDT postscaler value (from WDTCONbits.RMPS)
The Run mode WDT counter is reset on:
- Any device Reset
- Execution of WDT_CLEAR Instruction within the allowed window
- On the occurrence of a WDT Event, while WDT reset mode is disabled (FWDT.WDTRSTEN = 0)
- Disabling WDT by clearing the ON bit of the WDTCON register
- Execution of a DEBUG command
Watchdog Timer Window
The WDT has an optional Windowed mode that is enabled by clearing the WINDIS bit (WDTCON[0]). In the Windowed mode (WINDIS = 0), the WDT must be cleared only within the allowed window interval of the WDT time-out period, as shown in the accompanying image.
There is an option to select the size of the window where the WDT should be cleared based on the Watchdog Window Select bits.
(WINSIZE[1:0]) in the WDTCON register. The bit settings are as follows:
- 11 = WDT Allowed Window is 25 percent of the WDT period
- 10 = WDT Allowed Window is 37.5 percent of the WDT period
- 01 = WDT Allowed Window is 50 percent of the WDT period
- 00 = WDT Allowed Window is 75 percent of the WDT period
If the WDT is cleared before the allowed window, a system Reset is generated immediately.
The Windowed mode is useful for resetting the device during unexpectedly quick or slow execution
of a critical portion of the code.
Power Save Mode WDT
When the device is awakened from Power-Saving mode by a WDT time-out or a non-WDT NMI interrupt,ย the Power-Saving mode WDT counter is held in reset, and the WDT run mode continues counting from the count value that was saved when the device went into Power-Saving mode.
A WDT Sleep/Idle mode event can also trigger a WDT interrupt on wake-up from Sleep/Idle mode if IEC0[WDTIE] is enabled.
If the WDT Interrupt Enable bit, WDTIE, is cleared, an interrupt will not be generated on the WDT wake-up event. However, the WDTIF bit will still be set if an interrupt condition occurs. The user canย clear the interrupt in the Interrupt Service Routine (ISR) by clearing WDTIF.
Application Example
The Sleep/Idle mode WDT may be used to accomplish tasks at regular intervals of time while the device is put to Sleep/Idle mode between these regular intervals.
