dsPIC33A Power-Saving Modes
Overview
The dsPIC33A family devices provide the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of peripherals being clocked constitute lower power consumption. This page describes the power-saving modes implemented in dsPIC33A devices.
The dsPIC33A device family offers a number of built-in capabilities that allow user applications to select the best balance of performance and low-power consumption.
Power-Saving Features
- Instruction-based power-saving modes
- Peripheral Module Disable (PMD)
- Clock frequency and clock switching
Combinations of these methods can be used to selectively tailor an application’s power consumption while still maintaining critical application features, such as timing-sensitive communications.
Instruction-Based Power-Saving Modes
The dsPIC33A family of devices can operate in two instruction-based power-saving modes, Sleep and Idle. These modes can be entered by executing a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution. Idle mode halts the CPU and code execution but allows peripheral modules to continue operation. The assembler syntax of the PWRSAV instruction is shown here in assembly and C language:
Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device reset. When the device exits these modes, it is said to wake up.
Sleep Mode Operation
- It is the lowest current consumption mode
- The CPU and most peripherals are halted
- Select peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep
- If enabled, WDT operating using LPRC clock continues to run
- Primary oscillator, auxiliary oscillator, and Fail-Safe Clock Monitor (FSCM) are disabled
When the device exits Sleep mode, the CPU starts executing instructions within eight system clock cycles. The system clock and peripheral clock are re-enabled. The device restarts with the current clock source as indicated by the Current Clock Source Selection bits (COSC[2:0]) in the Oscillator Control register (OSCCTRL[2:0]).
Idle Mode Operation
Idle mode halts the CPU and code execution but allows peripheral modules to continue operation.
- The CPU stops executing instructions.
- The system clock source remains active.
- By default, peripherals continue to operate normally from the system clock source. Optionally, the peripherals can be shut down using their Stop-in-Idle (SIDL) control bit
Peripheral Module Disable (PMD)
All peripheral modules (except for I/O ports) in dsPIC33A devices have a control bit that can be selectively disabled to reduce power consumption. These bits, known as the Peripheral Module Disable (PMD) bits, are generically named “xxxMD” (where “xxx” is the mnemonic version of the module’s name). These bits are located in the PMDx Special Function Registers (SFRs). The PMD bit must be set (= 1) to disable the module. The PMD bit completely shuts down the peripheral, effectively powering down all circuits and removing all clock sources. By default all peripherals are not disabled by PMD.
Clock Frequency & Clock Switching
The dsPIC33A family devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by setting NOSCx bits (OSCCON[10:8]) and setting the OSCSWEN bit, as well as addressing any CLKxDIV changes required.
The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in the oscillator chapter of the device data sheet.