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dsPIC33A Reset Module

Last modified by Microchip on 2025/09/19 13:43

Overview

The dsPIC33AK512MPS512 family of devices implements a reset module to safely control device start-up, faults and external conditions. An internal System Reset (SYSRST) signal may be generated from multiple reset sources, such as Power-on Reset (POR), Brown-out Reset (BOR), Master Clear Reset (MCLR), watchdog time-out, Software Reset (SWR) and Configuration Mismatch Reset (CM). A simplified block diagram of the reset module is shown in Figure 1:

reset system diagram

Figure 1

There are two types of system resets: cold reset and warm reset. A cold reset is the result of a Power-on Reset (POR) or Brown-out Reset (BOR). A warm reset is the result of all other reset sources, including the RESET instruction.

Cold Resets

  • Power-on Reset (POR)
  • Brown-out Reset (BOR)

Warm Resets

  • Master Clear Reset (MCLR)
  • Watchdog Time-out Reset (WDT)
  • Software Reset (SWR)
  • Configuration Mismatch Reset (CM)

Power-On Reset (POR)

A POR circuit ensures the device is reset from power-on. The POR circuit is active until VDD crosses the VPOR threshold, and the power-up delay, TPU has elapsed.

reset POR signals

Figure 2

A power-on event generates an internal POR pulse when a VDD rise is detected above VPOR. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR pulse. In particular, VDD must fall below VPOR before a new POR is initiated. For more information on the VPOR and VDD rise-rate specifications, refer to the device data sheet. A POR event can also be generated when the 1.1V core voltage drops below a safe operating condition.

The POR bit in the Reset Control (RCON[0]) register is set to indicate the POR.

Information

When the device exits the reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges; otherwise, the device will not function correctly. The user software must ensure that the delay between the time power is first applied and the time the system reset is released is adequate to get all operating parameters within the specification.

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Brown-out Reset (BOR)

The BOR module generates a device reset when a brown-out condition occurs to protect against code misexecution. The BOR module is based on an internal voltage reference circuit that monitors VDD. Brown-out conditions are generally caused by glitches on the AC mains (for example, missing portions of the AC cycle waveform due to bad power transmission lines or voltage sags due to excessive current draw when a large inductive load is turned on).

reset BOR signals

Figure 3

A BOR generates a reset pulse that resets the device. The BOR status bit (RCON[1]) is set to indicate that a BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle mode and resets the device should VDD fall below the BOR threshold voltage. The BOR threshold voltage is detailed in the electrical characteristics section of the data sheet.

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Master Clear Reset (MCLR)

Whenever the master clear pin (MCLR) is driven low, the Reset event is synchronized with the System Clock (SYSCLK) before asserting the System Reset (SYSRST), provided the input pulse on MCLR is longer than a certain minimum width, as specified in the Electrical Characteristics section of the datasheet.

reset MCLR signals

Figure 4

The MCLR pin provides a filter to minimize the effects of noise and to avoid unwanted Reset events. The Status bit, EXTR (RCON[7]), is set to indicate the MCLR Reset.

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Watchdog Time-out Reset (WDT)

Whenever a watchdog time-out occurs, the device will asynchronously assert SYSRST.

reset WDT signals

Figure 5

A watchdog time-out during Sleep or Idle mode will wake up the device, but will not reset the device. The watchdog time-out flag bit in the Reset Control register (RCON[4]) is set to indicate the watchdog reset.

Information

The watchdog timer is reset, and the Run mode WDT counter is cleared by any of the following circumstances:

  • Any device reset
  • Execution of the WDT_CLEAR instruction
  • Disabling WDT by clearing the ON bit of WDTCON register
  • Execution of a DEBUG command

Visit the "dsPIC33A Watchdog Timer (WDT) Peripheral" peripheral page to learn more about this peripheral.

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Software Reset (SWR)

Whenever the RESET instruction is executed, the device will enter a warm reset state. The device will be released from a reset state at the next instruction cycle, and the reset vector fetch will commence. The Software Reset (Instruction) Flag bit (SWR) in the Reset Control register (RCON[6]) is set to indicate the software reset.

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Configuration Mismatch (CM)

To maintain the integrity of the stored configuration values, all device configuration bits are loaded and implemented as a complementary set of bits. As the configuration words are being loaded, for each bit loaded as 1, a complementary value of 0 is stored into its corresponding background word location and vice versa. The bit pairs are compared every time the configuration words are loaded, including Sleep mode. During this comparison, if the configuration bit values are not found opposite to each other, a configuration mismatch event is generated, which causes a device reset.

If a device reset occurs as a result of a CM reset, the CM status bit (RCON[9]) is set.

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