Oscillators

Last modified by Microchip on 2026/10/19 09:36

The following diagram outlines the oscillators available to the dsPIC33A Clocking System:

Diagram of oscillators available to the dsPIC33A Clocking System

On Power-on Reset (POR), Brown-out Reset (BOR), or any Reset event, the internal 8 MHz Fast RC (FRC) oscillator is automatically selected as the default system clock source, providing fast and reliable device startup.

The FRC oscillator is always enabled after Reset and continues to drive the CPU clock until the application switches to another oscillator source.

Oscillator Types

The following table summarizes the key performance features of the four oscillator types:

oscillator types table

Always refer to the product data sheet for all electrical specifications.

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FRC/BFRC Oscillator Tuning

The FRC and Backup Fast RC (BFRC) oscillators are factory calibrated at 25°C and 3.3V

Application software can further compensate for temperature or voltage drift using tuning registers:

  • FRCTUN[5:0] — FRC oscillator tuning
  • BFRCTUN[5:0] — BFRC oscillator tuning

The following table provides a greater insight into the TUN[5:0] bits and tuning range:

TUN[5:0] bits and tuning range table

  • The calibrated target frequency is 8 MHz
  • Software can fine-tune the oscillator frequency as needed
  • Each TUN bit step adjusts the frequency by approximately 10.5 kHz
  • Setting the TUN bits to ‘000000’ restores the factory-calibrated frequency

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POSC Modes of Operation

The following table reviews the Primary Oscillator (POSC) operating modes supported by the dsPIC33A device family:

Primary Oscillator (POSC) operating modes table

Always refer to the product data sheet for all electrical specifications.

The Primary Oscillator supports three operating modes:

  • XT Mode — for medium-frequency crystals or resonators
  • HS Mode — for high-frequency crystals or resonators
  • EC Mode — for an external clock source input

Each mode is optimized for different clock source types and frequency ranges, allowing flexibility for various application requirements.

The operating mode is selected using the Primary Oscillator Mode (POSCMD) and Primary Oscillator I/O Function (POSCIOFNC) configuration bits in the Oscillator Configuration (OSCCFG) register.

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POSC Features for Robust Operation

Different crystals require different oscillator drive strengths for reliable operation and startup. The POSC hardware provides Oscillator Gain Control to adjust the oscillator drive strength as needed.

Key points:

  • Gain controls the oscillator driver transconductance, measured in mA/V
  • Gain is configured using OSCCFGbits.GAIN[1:0] as shown in the table below
  • Select the minimum gain required for stable oscillator operation

OSCCFGbits.GAIN[1:0] table

Always refer to the product data sheet for all electrical specifications.

The device also supports a KICKSTART feature to improve oscillator startup reliability.

KICKSTART operation:

  • Temporarily boosts oscillator drive strength during startup
  • Helps crystals start oscillating faster and more reliably
  • Enabled using OSCCFGbits.KICKSTART as shown in the following table

POSC robust operation kickstart table

For proper configuration:

  • Use the oscillator electrical specifications to determine the recommended gain and transconductance values
  • Combine Gain Control and KICKSTART as needed for reliable crystal startup and stable operation

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Crystal Oscillator and Resonator Start-Up

Crystal Oscillator and Resonator startup time is determined by two key timing parameters:

  • TOSCD — Oscillator Start Delay
    • Time required for the crystal or resonator to begin oscillating
  • TOST — Oscillator Stabilization Timer
    • A 10-bit timer that waits for 1024 oscillator cycles to ensure stable operation

The total oscillator startup time is:

  • TOSCD + TOST

Refer to Figure 1 for typical oscillator and resonator start-up information.

During:

  • POR
  • BOR
  • Wake-up from Sleep

Both TOSCD and TOST must complete before the oscillator is considered stable and ready for operation in XT or HS modes.

Osc startup

Figure 1

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