Packaging for Silicon Carbide
Gate Drive Return Path
Let's discuss packaging and its importance in Silicon Carbide (SiC) devices. One of the key advantages of SiC is its ability to switch very quickly. However, fast switching can lead to undesirable effects from parasitic inductance and capacitance.
Consider a typical TO-247 package shown in the accompanying Figure 1. This package includes gate, drain, and source pins, as well as the die and the bond wires that connect to it. The drain is connected to the back of the die and does not require bond wires, whereas the source and gate do require bond wires to connect the die to the pins.
Figure 1: Gate Drive Return Path
In a TO-247 package, the parasitic inductance from the die to the source is typically around 10 nH. This parasitic inductance can impact the performance of SiC devices, especially during fast-switching events. Therefore, minimizing these parasitic elements is crucial for optimizing the performance and reliability of SiC devices.
Understanding the packaging and its associated parasitic elements helps in designing circuits that can fully leverage the advantages of SiC, such as high efficiency and fast switching, while mitigating potential issues related to parasitic inductance and capacitance.
Common Source (3-lead)
This slide focuses on the impact of packaging, specifically the common source inductance in a 3-lead MOSFET package, on the performance of the MOSFET circuit. Refer to Figure 2.
Figure 2: Common Source
Key Points
- Voltage Development Across Common Source Inductance:
- The slide illustrates how voltage can develop across the common source inductance due to current flowing through the lead.
- Using the example provided:
- Inductance (L) = 10 nH
- Change in current (di) = 50A
- Change in time (dt) = 50 ns
- The voltage developed (V_L) can be calculated using the formula:
- This means a 10V voltage can develop across the common source inductance due to the rapid change in current.
- Impact on MOSFET Control:
- This parasitic voltage perturbation opposes the gate-to-source voltage (V_GS) that is trying to control the MOSFET's on/off state.
- When the MOSFET is switching, the voltage developed across the common source inductance can interfere with the intended V_GS, potentially causing instability or improper switching.
- This opposition can lead to inefficiencies and reduced performance, as the MOSFET may not switch as intended due to the parasitic voltage
Summary
This emphasizes the importance of understanding and mitigating the effects of common source inductance in MOSFET packaging. The example calculation shows how significant voltage can develop across the inductance, which can interfere with the MOSFET's operation. Proper design and packaging considerations are essential to minimize these parasitic effects and ensure reliable and efficient MOSFET performance.
Kelvin Source (4-lead)
When a MOSFET turns on and current begins to increase through the source pin, the inductance in the circuit causes a voltage to appear across it. Refer to Figure 3. For instance, with a relatively slow rate of change in current (dI/dT) of 1A per nanosecond and an inductance of 10 nH, this would generate a voltage of 10V across the parasitic inductance. This voltage opposes the gate voltage (V_GS) that is intended to turn the MOSFET on, resulting in a slower turn-on time. Essentially, this acts as a form of negative feedback, reducing the driver's ability to quickly switch the MOSFET.
Figure 3: Kelvin Source
To mitigate this issue, a four-lead TO-247 package with a different pin configuration, shown in Figure 3, is often used for SiC devices. This package includes what is known as a Kelvin source, or a source pin that is directly connected to the die and used by the gate driver circuit. By connecting the gate drive circuit directly to this Kelvin source, the 10 nH of inductance, along with the bond wire and pin inductance, is effectively bypassed. This eliminates the dI/dT-induced voltage across the inductance, allowing the MOSFET to turn on and off more quickly.
This configuration offers additional advantages, such as improved routing for the gate drive circuit and a much smaller gate loop, which reduces parasitic inductance. Furthermore, it increases the distance between the high-voltage drain and the low-voltage gate and source pins, enhancing creepage distance. This allows the device to operate more reliably at higher voltages.