PolarFire® SoC Applications - FPGA Design, Creating and Programming
PolarFire SoC Applications: FPGA Design, Creating, and Programming
Here, we will create a Libero® project, run through Design Flow, and program the Field-Programmable Gate Array (FPGA). Design Flow is a sequence of steps that must be completed before programming the design into the FPGA. These steps convert the design components into a gate-level netlist, map the netlist to FPGA physical resources, and generate a programming image for the FPGA. This topic shows how to pass through Design Flow for the PolarFire® System on Chip (SoC) Discovery Kit, but using this guide, you will understand how to pass flow for any PolarFire SoC.
Contents
Libero SoC Design Flow
Creating a Libero Project
Creating a Project
Open Libero SoC, and navigate to Project > New Project or press Ctrl + N. It should open the New Project wizard.
Configure Project Name
Specify your project name in the Project name field and specify the folder where you want to create the project. Then click Next.
Configure Project SoC
In this tab, you need to find your SoC.
Search MPFS095T-1FCSG325E for the Discovery Kit.
Select the part and click Finish.
Importing MSS Component and Creating SmartDesign®
Import the MSS Component to the Project
To import MSS, go to the Design Flow tab and double-click on the first option, Import MSS.
Select the CXZ file that was generated from the MSS configurator.
Creating SmartDesign
In the Design Flow tab, double-click on the Create SmartDesign option.
You will see the following window.
Name your design "DesignTop" and click OK.
Setting Root Component
Move to the Design Hierarchy tab and right-click on the DesignTop, then choose the Set as Root option.
Now, you will see the message Top Module (root): DesignTop.
Importing MSS to the Smart Design
Now, in the Design Hierarchy tab, you will see SmartDesign and MSS. Drag and drop the MSS component into the SmartDesign.
Now, in SmartDesign, you have the visual representation of the MSS component.
Clock Conditioning Circuitry (CCC) Installation
Clock conditioning circuitry is required in our design because CCC helps:
- Reduce jitter and noise: Ensures stable, reliable clock signals for accurate timing
- Generate multiple frequencies: Allows creation of different clock domains from one source
- Manage phase and skew: Aligns clock signals for synchronous operation
To add the CCC component, switch to the IP Catalog tab, search for Clock Conditioning Circuitry (CCC), and confirm the creation of the component with the default name.
Drag and drop the core to SmartDesign. Core configurator will open.
Open Clock Options PLL tab and change Input Frequency to 160 MHz.
Switch to the Output Clocks tab, and change Requested Frequency to 125 MHz, then click OK. Confirm warning and info messages.
PolarFire RC Oscillator Installation
The RC OSC can be used to generate a startup clock or low-frequency reference clock, but for jitter considerations and accuracy, an external oscillator should be used to provide a reference clock for fabric logic. To add the RC OSC to our design in the Catalog tab, search for PolarFire RC Oscillators, drop it on SmartDesign, and confirm the creation of the component with the default name.
Copy the configuration and click OK. Confirm warning and info messages.
PolarFireSoC Initialization Monitor Installation
In the Catalog tab, search for PolarFireSoC Initialization Monitor and drop it on SmartDesign. Confirm the created component with the default name.
Copy the configuration and click OK. Confirm warning and info messages.
CoreReset_PF Installation
In the Catalog tab, search for CoreReset_PF and drop it on SmartDesign. Confirm the created component with the default name. There is nothing to configure, so just click OK and confirm the warning and information messages.
SmartDesign Connection
To create a connection between instances, , and in Libero SoC, press Ctrl + U. You should see the window in the accompanying image. Click on the ellipsis button (...) and choose the downloaded TCL file, and click Run to execute the script.
You should see this message after execution. Click Close to close the window. Now in SmartDesign press Ctrl+S to save file.
Your SmartDesign layout should look like this:
Generating Component and Building Hierarchy
In the Design Hierarchy, right-click on the DesignTop and choose the Generate Component option.
Click on the Build Hierarchy button, and the ⚠️ icon should disappear.
Timing and Synthesis
Timing Constraints Management
To open Constraints Manager, navigate to the Design Flow tab and double-click on the Manage Constraints option.
Now navigate to the Timing tab in the Constraints Manager tab.
Now, click on the Edit drop-down and select the Edit Synthesis Constraints option. The constraint editor will open. Double-click on the first option to create a new constraint.
Copy the parameter as shown and click on the ellipsis (...) button.
Search for REFCLK* pattern.
Select REFCLK and click on the Add button, then click OK. Click OK again, then press Ctrl + S to save and close the window.
You'll have this view. Now, click the Derive Constraints button and in the message popup, click Yes. Now enable all checkboxes for Place and Route and Timing Verification to have this view.
Save the changes by clicking on the Save button in the top right corner.
Synthesis
To run the Synthesis tool, navigate to the Design Flow tab and double-click on Synthesize.
You should now have this view.
I/O Configuration and Place and Route
I/O Editor Management
Again, open the Constraints Manager, but now navigate to the I/O Attributes tab.
Open the Edit option drop-down menu and click on Edit with I/O Editor. The I/O editor will open.
Here we see that we have five unconnected pins. Four of them relate to SPI and one to reset.
- EXT_RST_N
- SPI0_CLK
- SPI0_MISO
- SPI0_MOSI
- SPI0_SS
MOSI is pin A18, MISO is E11, CS is C16, and CLK is E17, so let's enter that information into the pin number section.
Connect the EXT_RST_N to the T19 pin, which is the push button on the board. By clicking on it, you'll reset the board.
Finally, save your changes by pressing Ctrl + S. That's all you need to do; you can now close the window and return to the Design Flow tab.
Place and Route
Navigate to the Design Flow tab and double-click on the Place and Route tool. You will see this in the Design Flow tab:
Timing and Power Analysis
Timing Verification
To run the Timing verification tool, run the Verify Timing from the Design Flow tab.
If your design has the correct configurations and constraints, you should see this in your Design Flow tab.
Power Verification
To run the Power verification tool, run the Verify Power tool from the Design Flow tab.
If your design has the right configurations and constraints, you should see this in your Design Flow tab.
Program Design
Generate FPGA Array Data
Now, we need to generate FPGA array data to continue. To generate it, double-click on the Generate FPGA Array Data button in the Design Flow tab.
If everything is correct, you will see this in your Design Flow tab.
Generate Design Initialization Data
Now, we need to generate design initialization data to continue. To generate it, double-click on the Generate Design Initialization Data button in the Design Flow tab.
If everything is correct, you should see this in your Design Flow tab.
Generate Bitstream
Now we need to generate a bitstream to continue. To generate it, double-click on the Generate Bitstream button in the Design Flow tab.
You should see this in your Design Flow tab:
Run PROGRAM Action
Finally, let's program the SoC. To program the SoC, double-click on the Run PROGRAM Action button in the Design Flow tab. It opens the warning pop-up.
Warning message:
You've successfully programmed the device with your own Fabric and MSS configurations.
