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8-bit Device Limitations - 10F/12F/16F Families

Last modified by Microchip on 2023/11/10 11:03

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These are the Debug and Programming limitations for the PIC 8-Bit Families 10F,12F, and 16F.

PIC10F2XX, PIC12F5XX, PIC16F5XX Limitations

  • PIC16F505, PIC12F509, PIC12F508, PIC10F206, PIC10F204, PIC10F202, and PIC10F200.
  • PIC16F506, PIC12F510, PIC10F222, and PIC10F220.
  • PIC16F526 and PIC12F519.
  • PIC16F527.
  • PIC16F570.

Headers are required for debugging when using these devices. See the “Processor Extension Pak and Debug Header Specification” for details. Header limitations are as follows:

  • Debug and Programming Limitations - PIC® MCUs
  • You cannot single step through an interrupt. Due to hardware restrictions, the debugger/emulator cannot jump to the interrupt vector memory location in Single Step mode.
  • TRISIO and OPTION_REG are available in the Watch window but not accessible. TRISIO and OPTION_REG are available in the Watch window SFR list, but neither is accessible and will always show a value of 0.
  • Program memory standard Flash. Program memory not enhanced Flash. You cannot program in Low Voltage mode (Vdd < 4.5 V.) See the device programming specification, for more information.

Freeze on Halt Limitations

  • Freeze on Halt is not supported.

PIC16F505 Only

  • MPLAB hardware debuggers do not display correct values for TRISC in the SFR window since this SFR is not addressable.

PIC16F570 Only

  • For PIC16F570 (AC244062), there is no debug visibility into GPR banks 4, 5, 6, and 7, although user access to these banks works.

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PIC12F629/675 Limitations

Headers are required for debug when using the listed devices. See the “Processor Extension Pak and Debug Header Specification” for details. Header limitations are as follows:

  • Debug and Programming Limitations - PIC® MCUs
  • You cannot single step through an interrupt. Due to hardware restrictions, the debugger/emulator cannot jump to the interrupt vector memory location in Single Step mode.
  • Cannot erase ID memory at Vdd < 4.5 V. At Vdd < 4.5 V, the part cannot be bulk erased, so it has to be row erased. Row erase can be used on program memory, but not on configuration memory (where user ID resides).
  • Program memory standard Flash. Program memory, not enhanced Flash. You cannot program in Low Voltage mode (Vdd < 4.5 V). See the device programming specification for more information.
  • RBIF is cleared when PORT is interrogated by software, except when Freeze on Halt is enabled.
  • This header cannot be programmed while the GP1/RA1 pin is high (VIH) due to an –ICD debug silicon issue. There are two workarounds:
  • (1) Move the circuitry that makes GP1/RA1 high to another I/O pin during programming.
  • (2) Manually make GP1/RA1 low during programming (for debuggers/emulators that can supply power to the target):
    • Disconnect the header from the target circuit.
    • Select File > Project Properties, click the debugger, and select Power from the Option categories menu. Check the Power target circuit from… box if it is not already checked.
    • Connect GP1 to Vss on the header.
    • Select Debug > Discrete Debugger Operation > Build for Debugging.
    • Select Debug > Discrete Debugger Operation > Program Device for Debugging.
    • Disconnect GP1 from Vss on the header.
    • If you were NOT using a debug tool to power your target board, select File > Project Properties, click the debugger, and select Power from the Option categories menu. Uncheck the Power target circuit from… box if it is checked.
    • Insert the header into the target board.
    • Code is now programmed into the device and ready to be debugged. Select Debug > Discrete Debugger Operation > Launch Debugger.
    • Repeat the process to reprogram the device.

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Freeze on Halt Limitations

  • Timer0 will not freeze using the internal clock.
  • CMOUTx pins do not freeze, status bits and interrupt flags do freeze.
  • RBIF is cleared when PORT is interrogated by software, except when Freeze on Halt is enabled.

For PIC12F675-ICD (AC162050) Only

  • GP1 should be pulled low for this header; otherwise, you might not be able to program and debug using the header.

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PIC12F635/683, PIC16F63X/68X Limitations

  • PIC12F683
  • PIC12F635
  • PIC16F636
  • PIC16F639
  • PIC16F684
  • PIC16F688

Headers are required for debugging when using these devices. See the “Processor Extension Pak and Debug Header Specification” for details. Header limitations are as follows:

  • Debug and Programming Limitations - PIC® MCUs
  • You cannot single step through an interrupt. Due to hardware restrictions, the debugger or emulator cannot jump to the interrupt vector memory location in Single Step mode.
  • Cannot erase ID memory at Vdd < 4.5 V. At Vdd < 4.5 V, the part cannot be bulk erased, so it has to be row erased. Row erase can be used on program memory, but not on configuration memory (where user ID resides).
  • Program memory standard Flash. Program memory not enhanced Flash. You cannot program in Low Voltage mode (Vdd < 4.5 V). See the device programming specification for more information.

PIC16F636 Family Only

  • Above 16 MHz, in External Clock input (EC) mode, an MPLAB IDE Reset executes the first few instructions instead of only one instruction. The workaround is to add three No Operations (NOPs) at the reset vector.

PIC16F684-ICD Only

  • Cannot communicate with an AC162055 below 3.375 V and cannot erase USER ID below 4.5 V. You can program and debug at 2.0 V if you start with an erased header (erased at a higher voltage).

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Freeze on Halt Limitations

  • Timer0 will not freeze using the internal clock.
  • CMOUTx pins do not freeze, status bits and interrupt flags do freeze.

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PIC16F616 Family Limitations

  • PIC16F616
  • PIC16F610
  • PIC12F615
  • PIC12F617
  • PIC12F609
  • PIC16HV616
  • PIC16HV610
  • PIC12HV615
  • PIC12HV609

Headers are required for debugging when using these devices. See the “Processor Extension Pak and Debug Header Specification” for details. Header limitations are as follows:

  • Debug and Programming Limitations - PIC® MCUs
  • You cannot single step through an interrupt. Due to hardware restrictions, the debugger/emulator cannot jump to the interrupt vector memory location in Single Step mode.
  • Cannot erase ID memory at Vdd < 4.5 V. At Vdd < 4.5 V, the part cannot be bulk erased, so it has to be row erased. Row erase can be used on program memory, but not on configuration memory (where the user ID resides).
  • Self read/write is not supported for the PIC12F617 device.
  • ECCP Capture mode interrupts do not occur when emulating the PIC12F615 and PIC12F617 devices.
  • Program memory standard Flash. Program memory not enhanced Flash. You cannot program in Low Voltage mode (Vdd < 4.5 V.) See the device programming specification for more information.

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Freeze on Halt Limitations

  • Freeze on Halt is not supported.

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PIC16F630/676 Limitations

Headers are required for debug when using these devices. See the “Processor Extension Pak and Debug Header Specification” for details. Header limitations are as follows:

  • Debug and Programming Limitations - PIC® MCUs
  • You cannot single step through an interrupt. Due to hardware restrictions, the debugger/emulator cannot jump to the interrupt vector memory location in Single Step mode.
  • ID memory cannot be erased at Vdd < 4.5 V. At Vdd < 4.5 V, the part cannot be bulk erased, so it has to be row erased. Row erase can be used on program memory, but not on configuration memory (where user ID resides).
  • Program memory standard Flash. Program memory, not enhanced Flash. You cannot program in Low Voltage mode (Vdd < 4.5 V). See the device programming specification for more information.
  • RBIF is cleared when PORT is interrogated by software, except when Freeze on Halt is enabled.

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Freeze on Halt Limitations

  • Timer0 will not freeze using the internal clock.
  • CMOUTx pins do not freeze, status bits and interrupt flags do freeze.

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PIC16F648A Family Limitations

  • PIC16F648A
  • PIC16F628A
  • PIC16F627A

Headers are required for debugging when using these devices. See the “Processor Extension Pak and Debug Header Specification” for details. Header limitations are as follows:

  • Debug and Programming Limitations - PIC® MCUs
  • You cannot single step through an interrupt. Due to hardware restrictions, the debugger or emulator cannot jump to the interrupt vector memory location in Single Step mode.
  • Program memory standard Flash. Program memory, not enhanced Flash. You cannot program in Low Voltage mode (Vdd < 4.5 V). See device programming specification for more information.
  • RCIF is cleared when RCREG is interrogated by software, except when Freeze on Halt is enabled.
  • RBIF is cleared when PORT is interrogated by software.
  • When driving a clock oscillator of more than 4 MHz into OSC1 in HS Oscillator mode, the device will not go into Debug mode, therefore, crystal caps will be required. The 32 kHz to 4 MHz range does not have this issue.
  • Above 16 MHz, in External Clock input (EC) mode, a Reset executes the first few instructions instead of only one instruction. The workaround is to add three NOPs at the reset vector.

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Freeze on Halt Limitations

This device family requires a header for debugging. Header limitations are as follows:

  • Timer0 will not freeze using the internal clock.
  • Timer0 will not freeze using the external clock.
  • CMOUTx pins do not freeze, status bits and interrupt flags do freeze.

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PIC16F690 Family Limitations

Headers are required for debugging when using these devices. See the “Processor Extension Pak and Debug Header Specification” for details. Header limitations are as follows:

  • Debug and Programming Limitations - PIC® MCUs
  • You cannot single step through an interrupt. Due to hardware restrictions, the debugger or emulator cannot jump to the interrupt vector memory location in Single Step mode.
  • You cannot erase ID memory at Vdd < 4.5 V. At Vdd < 4.5 V, the part cannot be bulk erased, so it has to be row erased. Row erase can be used on program memory but not on configuration memory (where the user ID resides).
  • PIC16F690-ICD Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) Issues: Both the production devices and ICD versions of the devices have the same EUSART issues. Please refer to errata DS80243 for more information and workarounds.
  • Program memory standard Flash. Program memory not enhanced Flash. You cannot program in Low Voltage mode (Vdd < 4.5 V.) See the device programming specification for more information.
  • BF is cleared when SSPBUF is interrogated by software. Above 16 MHz, in External Oscillator (EC) mode, a Reset executes the first few instructions instead of only one instruction. The workaround is to add three NOPs to the reset vector.

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Freeze on Halt Limitations

  • Timer0 will not freeze using the internal clock.
  • CMOUTx pins do not freeze, status bits and interrupt flags do freeze.

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