Level 3 Topology Control

Last modified by Microchip on 2024/01/15 19:51

Level 3 Topology Control Integration allows the standard analog design to be reconfigured, in addition to the Level 1 and Level 2 features. This includes changing the analog loop configuration and swapping between two different analog control loop filters. The accompanying figure shows an example. The power supply can change from a PWM control loop to a hysteretic control loop when a load change is expected. The controller may be tuned for high performance, which allows fast response to those load changes. Once the change is completed, the system can then enter a High Efficiency mode, reducing dynamic performance, and increasing the system efficiency. At light load, this change would allow a continuous inductor current design to operate in discontinuous conduction mode, maintaining system efficiency.

level 3 block diagram

Figure 1

Switching frequency adjustment and dead time control can also be used to minimize losses. Microchip’s entire range of PIC® MCUs and DSCs can assist in Level 3 control applications.

In particular, Flash microcontrollers such as PIC16F785 and PIC16HV785 integrate MCU with analog peripherals and are well-suited for topology control. The device has two analog PWM modules that can control power stages. Two error amplifiers and two high-speed comparators can be connected to the PWM modules in many ways through digital configuration. All pins associated with the error amplifiers and comparators are available externally so any type of analog control loop can be created. Twelve ADC inputs are available to monitor power supply operating parameters. Figure 2 shows an LED lighting application example using PIC16HV785MCP1402 MOSFET driver, and MCP9700A temperature sensor.

level 3 LED application diagram

Figure 2

A Pulse Width Modulator (PWM), such as the MCP1630 and MCP1631 PWM controllers can be used to develop intelligent power systems, specifically for MCU power controller applications.

Figure 3 shows an application example using Microchip's family of Digitally-Enhanced Power Solutions offering a Programmable, Hybrid Power Controller combining a mid-voltage analog power stage (including analog control loop, MOSFET drivers, and sensing) with a microcontroller, enabling a user-configurable power converter. In this example, MCP19111 is used to drive MCP87XXX series high-speed MOSFETs in a synchronous buck converter.

level 3 digital power diagram

Figure 3

Back to top

Level 3 Topology Control Features List

Control

  • On/Off only, typically via a SHUTDN input to a traditional analog Switch Mode Power Supply (SMPS) controller
  • Proportional control of the SMPS performance, such as output voltage and current
  • Topology and Mode control, such as Buck-to-Boost for extended output range, continuous to discontinuous inductor current for zero output current capability, or the ability to add phases as needed

Back to top

Monitoring

Any available timing, analog, or digital signals available in the traditional analog SMPS. Including;

  • Current in/out
  • Voltage in/out
  • Temperature
  • PWM

Back to top

Possible Features

Features relying on On/Off control, such as:

  • Level 1 and Level 2 features
  • Continuous/discontinuous inductor current switching
  • Multiple loop filter options
  • Bypass for low battery operation
  • Topology shifts for better efficiency and smaller magnetics

Back to top

Analog Access Requirements

  • Shutdown and startup control through a SHUTDN input
  • Control of reference inputs such as PWM clock, VREF, and ILIMIT
  • Analog and digital switching of functional blocks in SMPS design
  • Analog, digital- and frequency-based signals for monitoring

Back to top

Reliability

Roughly half of the system reliability is still determined by the traditional analog SMPS design. However, now reliability software begins to dominate due to the possibility of invalid configurations and modes. In addition, switching time during mode and topology changes can introduce transient conditions leading to temporary instabilities.

Back to top

Reference

Back to top