# Digital Implementation of a Control Loop

Timing is very important in power conversion designs. The complete operation executed by the digital control loop, and the action that is consequently taken, introduce a delay. This delay is also present in analog designs. In the analog domain only small delays are to be considered. While in the digital domain, these delays are generally longer. The corresponding hardware/firmware is required to execute the set of instructions (commands) in a timely fashion. In digital design for example, to achieve the maximum possible bandwidth, it is useful to execute all the required operations within the duration of a PWM period. The speed of the core and peripherals allow the dsPIC^{®} DSC to update the controlled variables in a very short period.

The figure below summarizes the results and concepts of the digital implementation of the control loop. The PWM period is shown on the left. The ADC trigger located as shown, is at 50 percent of the active PWM output signal. Time T_{1} (680 ns) is required by the ADC to sample and convert the signal. At the end of this period, the new values are available and can be processed by the algorithm inside the dsPIC DSC. T_{2} (700 ns) is thus the overall time required to compute the updated duty cycle. Time T_{3} (100 ns) is the sum of other smaller delays that must be added to the loop timing, for instance, the PWM output delay.

Total time T_{to} = T_{1} + T_{2} + T_{3}, which is the overall time required by the system to generate a newly updated duty cycle value. Note that the times in the figure are examples only. Real durations vary according to the specific implementation.

It may seem that it takes considerably longer to process to the “computational” time required by the analog equivalent. Keep in mind that the sampling rate is related to the needed bandwidth of the system. If the sampling rate is 400 kHz, and we take a new sample every other period, the sampling frequency is 200 Kilosample(s) per second (Ksps). The overall system will perform well for a system bandwidth which is 1/10 of this frequency, approximately 32 kHz. Normally, in voltage mode and average current mode, we are interested in a signal that is slowly varying compared to the PWM. It also depends on how available the newly updated value for the converter duty cycle is. The position of this instant in time depends on the PWM period and other parameters.

- The new data can be either:
- Available within the duration of the current period, or
- Available in the following period. The effect of this results in the reduction of the converter bandwidth.