dsPIC® DSC Implementation of a PID Loop
Contents
Overview
Many different techniques can be used to implement a Proportional, Integral and Derivative (PID) loop in a dsPIC®. The approach that has been used in the current module is to introduce some advanced techniques to take the maximum possible advantage of the dsPIC itself. The reason for this is that in the production of a product, the designer is almost always finding ways to optimize the performance of the system, usually in terms of response time and transient response behavior.
You will become familiar with the relevant internal registers and will learn how to design with fast and efficient PID code. You will also learn how to squeeze the maximum accuracy from the system. The importance of getting the maximum accuracy will lead to maximum system performance.
The following figures present how a fast-, high-performance PID is implemented using the specific dsPIC hardware (DSP engine).
The architectural blocks used are:
- RAM, for storing coefficients and input error values
- Two 16-bit registers (W4 and W5) used to store data
- Two 16-bit registers (W8 andW10) to store pointers to RAM locations
- One 40-bit accumulator
The Coefficients area in RAM stores the Ka, Kb, Kc coefficients of the system. These values are fixed and will not be changed during the system operation.
The Errors area in RAM stores the error values. What is shown is the buffer status before a new PID output is computed (it will be understood later).
e(n-1) and e(n-2) are equal to zero at n=0; then they are updated at each step.
At time n, the accumulator contains the previous value of the PWM active period.
Below is the high-level block diagram of the PID implementation
dsPIC® Digital Signal Controllers (DSCs) Implementation Operations
The first operation is to set the two pointers to point at the first location of each buffer in the RAM. W8 in the following diagram is the pointer to the coefficients buffer; W10 is the pointer to the error buffer.
The new error value is computed as the difference between the reference voltage (Vref) and the new output voltage read by the Analog-to-Digital Converter (ADC) (ADCBUF1). See the accompanying image.
movsac Instruction
The movsac instruction performs several different tasks. The accompanying diagram and steps demonstrate the movsac instruction.
Move the RAM contents.
Update the Working registers.
Updates the W10 register so that it is now pointing to the following RAM location.
Proportional-Integral-Derivative (PID) Term Computation
Below are the computation steps of the first term of the PID.
The W4 and W5 registers' content is multiplied and the result is added to the 40-bit accumulator B.
Moves the content of the RAM location pointed by W10 into register W5.
Updates the W10 register so that it is now pointing to the following RAM location.
The W4 and W5 registers' content are multiplied and the result is added to the 40-bit accumulator B.
Moves the content of the RAM location pointed to by W10 into register W5.
Updates the W10 register, so that it is now pointing to the previous RAM location.
Store Accumulator Instruction
The accompanying diagram shows the operation of the store accumulator instruction, sac.r.
We store the high part (from 16th to 31st bit) of the accumulator into the W0 register. Before saving it, the value is shifted 8-bit positions to the left and the resultant value is rounded. See the accompanying diagram.
Copy the content of register W5 [that is e(n-1)] into the last location of the error buffer.
![Copy the content of register W5 [that is e(n-1)] into the last location of the error buffer.](/xwiki/bin/download/applications/power/dspic-33f-power-converter/pid-basics/dspic-implementation/WebHome/PID-operation-15.png?width=450&height=263&rev=1.1)
The content of the RAM location pointed to by [W10 -4] is then copied into the W5 register.
![The content of the RAM location pointed to by [W10 -4] is then copied into the W5 register.](/xwiki/bin/download/applications/power/dspic-33f-power-converter/pid-basics/dspic-implementation/WebHome/PID-operation-16.png?width=450&height=261&rev=1.1)
The pointer W10 is decremented, to point to the previous location of the error buffer
The content of register W5 (that is the current error e
) is stored in the RAM location pointed to by W10. The purpose of the operations performed in the last few diagrams is to make room for the next value of the error that will arrive in the next sampling period.
Example
The number of cycles required to perform the PID operations as indicated in the previous diagrams can be explained using the following example:
If the dsPIC DSC is running at 40 MIPS, each machine cycle equals 1/40 MHz = 25 ns. As a consequence, the total time required to perform the described task is 13 x 25 ns = 325 ns.
