High Speed USB

Last modified by Microchip on 2023/11/10 11:19


  • High speed USB was introduced in the year 2000 as part of the USB 2.0 specification.
  • The maximum theoretical bandwidth is 480 Mbit/s.
  • Uses four data lines - Power (5V), Ground, and two data lines (D+ and D-).
  • Half-duplex differential signaling on D+ and D-.
  • Uses traditional USB connectors.


High speed devices begin the enumeration process identical to full-speed devices. High speed devices announce to the host that they are ready to be enumerated by asserting a 5V signal on D+ through the use of a 1.5 kΩ pull-up resistor. During the 20 ms enumeration RESET signal sent by the host, the device executes the high-speed negotiation process. Upon completing this negotiation the device, host, and hub port connecting the device will operate in High-speed mode.

Differences with Full Speed USB


High speed USB was designed to coexist with full speed USB. The designers speculated many systems would have a host that could simultaneously offer support for full and high speed devices. To achieve compatibility, eight high-speed microframes are completed within 1 ms.

Full speed frame (high-speed microframes) diagram

Fm Sirame Size and Transfer Types

High Speed Frame Size: 125 μs

Supported Transfer TypesMaximuze of TransferTransfers per FrameMaximum Theoretical Throughput
Control64 bytes164 kByte/s
Interrupt1024 bytesup to 324 MByte/s
Bulk512 bytesup to 1353 MByte/s
Isochronous1024 bytesup to 324 MByte/s

USB Bus States and Signal Levels

High Speed USB

Bus States
Bus Levels
Differential "1"D+ high , D- low
Differential "0"D+ low , D- high
Single Ended 0 (SE0)D+ low , D- low
Single Ended 1 (SE1)D+ high, D- high Invalid condition!
Data J stateDifferential "1"
Data K StateDifferential "0"
IdleData J
ResumeData K
Start of Packet (SOP)switches from Idle to Data K
End of Packet (EOP)SE0 for 2 bits, followed by Data J for 1 bit
DisconnectSE0 >= 2 μs
ConnectIdle for 2.5 μs
ResetSE0 >= 2 μs

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