Hello FPGA
Libero® SoC Features
Libero Design Suite | Demo Overview |
Libero Design Tools
In this training, you will focus on Libero® SoC because it supports the latest Field Programmable Gate Array (FPGA) families. Your design entry methods include the SmartDesign® block-based tool, VHDL (Very High-Speed Integrated Circuit (VHSIC) Hardware Description Language (HDL)), Verilog, and SystemVerilog HDLs.
Libero SoC includes configurators for embedded blocks such as Phase-Locked Loops (PLLs), oscillators, or the SmartFusion® 2 microcontroller subsystem, and a library of free Intellectual Property (IP) cores. The ModelSim® Pro ME Simulator is included for simulation, and Synplify Pro® ME is included for synthesis.
Your place and route tools include Constraint Manager for entering constraints, such as pin assignments and I/O attributes, and the Chip Planner tool for floor planning or viewing logic placement. SmartTime and SmartPower are the Microchip timing and power analysis tools. FlashPro Express is the programming software you use to program the FPGA.
Libero SoC also includes two debug tools, SmartDebug and Identify ME, for on-chip debugging.
Figure 1 shows the development steps along with the corresponding design tool.

Figure 1: Libero Design Tools
Libero HDL Editor
Libero SoC's HDL editor shown in Figure 2, supports the creation and editing of Register Transfer Level (RTL) descriptions in VHDL 2008 and earlier, Verilog 2001 and earlier, and SystemVerilog. The editor includes color-coded VHDL and Verilog keywords, and a syntax checker to identify errors in your description.

Figure 2: Libero HDL Editor
IP Cores
Libero SoC includes a library of over 50 free IP cores, including processors, peripherals, and bus interfaces. Figure 3 shows a few of the IP cores available.

FIgure 3: Libero SoC IP Cores
You can configure and modify cores directly from Libero SoC. There's no need to launch separate tools. You can modify cores to change the existing configuration or the version. Figure 4 shows an example of modifying the on-chip RC oscillator.

Figure 4: Libero SoC Core Modification
Colored icons indicate the IP license status:
- Blank or no key - the core does not require a license.
- Green key - the core is fully licensed and supports the entire design flow.
- Yellow key - the core has a limited or evaluation license.
- Yellow key with a red circle - the core is not licensed for use.
Pre-compiled simulation libraries are provided, enabling you to instantiate and simulate the core. Clicking any core in the catalog displays a short summary of the core and links to the core release notes and handbook. See Figure 5 for how the colored icons appear in Libero SoC.

Figure 5: License Requirements
SmartDesign
SmartDesign is a block-based design entry tool that supports blocks from a variety of sources, such as HDL files, Microchip and third-party IP cores, and library cells. See Figure 6 to see how this appears in the application.

Figure 6: SmartDesign Block-Based Design
You add and configure objects in the design canvas as shown in Figure 7. Here you can make connections, and generate a synthesis-ready HDL file. SmartDesign supports all platforms and all families and performs design rule checks to confirm that there are no errors and that any special silicon design rules are honored.

Figure 7: Design Canvas
System Builder
System Builder, shown in Figure 8, is a design tool for SmartFusion 2 Arm®-based SoC designs that enables you to focus on your design specification without needing to know specific SmartFusion 2 silicon requirements. System Builder asks you basic questions about the desired system architecture to configure the SmartFusion 2 microcontroller subsystem and adds any required fabric peripherals based on the information you enter. The result is a correct-by-design complete system.

Figure 8: System Builder
ModelSim Simulator
The Mentor Graphics ModelSim Simulator, shown in Figure 9, allows you to verify your HDL description. ModelSim supports simulation at all levels: behavioral or pre-synthesis, structural or post-synthesis, and back-annotated timing simulation. The ModelSim Pro ME Simulator supports mixed-language simulation, meaning you can have a design with VHDL, Verilog, and SystemVerilog files.

Figure 9: ModelSim Simulator
Synopsys® Synplify Pro® ME
The Synopsys Synplify Pro ME synthesis tool, shown in Figure 10, optimizes your HDL design targeting any Microchip FPGA family. Synplify Pro ME can be launched directly from the Libero SoC project manager and supports mixed-language designs.

Figure 10: Synopsys Synplify Pro ME Synthesis Tool
SmartTime
SmartTime, shown in Figure 11, is Microchip's static timing analysis tool. It is used to perform a complete timing analysis of your design to ensure that all timing constraints are met and that the design operates with the desired amount of timing margin across all operating conditions.

Figure 11: SmartTime Static Timing Analyss Tool
SmartPower
SmartPower, shown in Figure 12, is Microchip's post-layout power analysis tool that displays the power consumption of your design. SmartPower provides static and dynamic power information for individual components in your design, such as nets, gates, I/O, and memory blocks. SmartPower supports a wide range of operating conditions for power analysis and generates detailed hierarchical power reports.

Figure 12: SmartPower Post-Layout Power Analysis Tool
SmartDebug
SmartDebug, shown in Figure 13, supports debugging the FPGA array and 3D blocks in Microchip SmartFusion 2, IGLOO® 2, RTG4™, and PolarFire® FPGAs. SmartDebug uses dedicated probe logic built into the FPGA fabric. It allows you to select two flip-flop outputs simultaneously and observe them on an oscilloscope or logic analyzer. Different probe points can be selected without recompiling your design. In addition, internal memory blocks can be read and modified.

Figure 13: SmartDebug using Dedicated Probe Logic
Eye Monitor
SmartDebug, shown in Figure 14, also supports debugging the high-speed serial interfaces in the SmartFusion 2, IGLOO 2, RTG4, and PolarFire FPGAs. It uses the on-chip Pseudorandom Binary Sequence (PRBS) features of the SerDes block to run different data patterns and allow adjustment of the signal integrity settings. For PolarFire FPGAs, SmartDebug supports the generation of the eye diagram at the receiver.

Figure 14: Eye Monitor for High-Speed Serial Interfaces
Synopsys Identify ME
Synopsys Identify ME, shown in Figure 15, is a debug tool for the Microchip flash FPGA families. It allows you to debug designs by probing internal signals at full system speed. Probe signals and a sample buffer are added at the HDL level before synthesis. Identify ME continuously captures data in the on-chip sample buffer. You can specify complex trigger conditions to control the data capture and view the results in a standard waveform viewer.

Figure 15: Synopsys Identify ME Debug Tool
Licenses
There are several licensing options for Libero SoC:
Free Licenses
- Silver
- Evaluation
Purchased Licenses
- Gold
- Platinum
- Standalone
Refer to the course syllabus for links to license information and software downloads.
Video Course
This course is also available in video format from Microchip University: Hello FPGA.