Hello FPGA

What is an FPGA?

Last modified by Microchip on 2025/01/22 10:05

   Get Started  Why use an FPGA?   

Objectives

Welcome to the Getting Started with Microchip Field Programmable Gate Arrays (FPGAs) training. If you have never used an FPGA and are wondering if an FPGA would be suitable for your next project, this class will help decide.

You will explore the progression of digital logic that led to the development of the first FPGAs and learn about their typical architectural features.

Small Scale Integration Logic (SSI)

Early integrated circuits were called Small Scale Integration (SSI). SSI devices implemented a single logic function, such as an AND gate, with fixed pin assignments. The table in Figure 1 shows some of the many SSI devices that were available. You would select devices from your TTL logic data book to implement your logic equations. The limited number of gates per package often resulted in the need to add additional packages for just one more gate, unless unused gates were available in other packages.

Single Logic Function chip digram

Figure 1: Small Scale Integration Logic

In Figure 2, you see a typical circuit board implemented using SSI devices that required many packages to implement logic functions.

Logic Board

Figure 2 Logic Board

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Programmable Array Logic (PAL)

In 1978, Monolithic Memories Incorporated (MMI) introduced a breakthrough device, the Programmable Array Logic (PAL). PAL devices have arrays of transistor cells organized in a programmable AND, fixed OR architecture as seen in Figure 3. Some PAL devices have flip-flops at the outputs. PAL devices have either synchronous or asynchronous feedback from the outputs. Some PAL devices are reprogrammable.

There are two types of reprogrammable PALs:

  • UV-erasable PALs that you erase by exposing them to UV light
  • PAL devices based on flash technology

PAL devices provided more integration and flexibility than SSI devices to implement digital circuits. PAL devices are sometimes referred to as Programmable Logic Devices (PLDs).

Programmable Array Logic

Figure 3: Programmable Array Logic

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Complex Programmable Logic (CPLD)

Extending the PLD concept further led to the creation of a Complex Programmable Logic Device (CPLD), shown in Figure 4. CPLDs comprise several simple PLDs with a programmable routing matrix to interconnect the logic blocks to each other and the I/O. CPLD devices offered 5,000 or more gates. A single CPLD could replace multiple PLD devices. One drawback of the CPLD architecture was the delay of the programmable routing matrix that was used to interconnect the simple PLD blocks.

Simple PLD Device

Figure 4: Complex Programmable Logic

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Field Programmable Gate Arrays

While PALs were being developed into CPLDs, a separate stream of development was happening based on gate array technology. These devices were called Field Programmable Gate Arrays (FPGAs). FPGAs have simpler logic blocks than PALs or CPLDs, and abundant routing resources to connect the logic elements together or to the I/Os. A Field Programmable Gate Array is an integrated circuit designed to be configured by you after the chip is manufactured, hence field programmable. FPGAs are fine-grain devices, meaning that they contain small logic blocks called Lookup Tables (LUTs), along with flip-flops.

The FPGA logic elements are organized in a grid similar to Figure 5.  Some FPGAs have hundreds of thousands of logic blocks. The I/O cells are found around the periphery of the device. FPGAs include abundant routing resources to connect the logic elements or to the I/O cells.

FPGA

Figure 5: Field Programmable Gate Arrays

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Logic Block

Figure 6 is a diagram of a typical logic block in an FPGA. It consists of an N-input LUT whose output feeds a flip-flop. The logic block output can be the LUT output or the flip-flop output, based on the configuration of the multiplexer.

FPGA Logic Block

Figure 6: Logic Block

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Look Up Table

A LUT is a small one-bit wide memory array with its address lines representing the inputs to the logic block and a one-bit output. An N-LUT can implement any logic function of N inputs. Figure 7 is an illustration of a four-input LUT. Configuration bits configure the LUT for the desired logic function and control the output multiplexer.

FPGA Logic Block

Figure 7: Logic Block

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Math Blocks

In addition to LUTs and flip-flops, modern FPGAs often contain math blocks for implementing digital signal processing designs, such as:

  • Finite Impulse Response (FIR) filters
  • Static Random Access Memory (SRAM) and Flash memory blocks
  • Phase-Locked Loops (PLLs)
  • Delay-Locked Loops (DLLs) for clock frequency synthesis and phase correction
  • Specialized I/O supporting high-speed I/O standards and high-speed transceivers
  • Embedded blocks such as microprocessors and peripherals
  • Analog blocks such as Analog-to-Digital Converters (ADCs) and Digital-to-Analog (DACs) converters

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Interconnects

The two most common interconnect technologies used in FPGAs are SRAM and Flash. SRAM-based FPGAs are based on static RAM technology. They're reprogrammable and volatile, meaning they have to be configured by you every time the device is powered. SRAM-based FPGAs often require an external boot device to hold the configuration.  Figure 8 shows the schematic of a re-programmable and volatile interconnect.

FPGA Interconnect

Figure 8: Interconnects

Flash-based FPGAs use a floating gate on a standard MOS transistor to make the interconnections in the device. Flash-based FPGAs are reprogrammable and non-volatile, meaning they don't have to be configured by you every time the device is powered. As a result, Flash-based FPGAs don't require an external boot device. Flash-based FPGAs are also lower power than SRAM-based FPGAs. Figure 9 shows a schematic of a non-volatile interconnect.

FPGA Flash Interconnect

Figure 9: Floating Gates

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Summary

In this training, you have been introduced to the evolution of digital logic from SSI logic to PALs to CPLDs to FPGAs, and some common features in FPGAs.  Figure 10 below, shows the evolution of the FPGA from SSI Logic to full FPGA.

Evolution from SSI to FPGA

Figure 10: Evolution of Digital Logic

Video training for this material is available at Microchip University:

Microchip Universtiy

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