Microchip FPGAs and SoCs

Last modified by Microchip on 2023/11/09 09:00

Microchip FPGA Families

Microchip's fourth and fifth generations of Field Programmable Gate Arrays (FPGAs) consist of three families:

FPGA Families

Shared benefits, features, and Intellectual Property (IP)

IGLOO®2, SmartFusion®2, and PolarFireTM Field Programmable Gate Arrays (FPGAs) share several common features and benefits:

  • Instant-on operation utilizing Non-Volatile Memory (NVM). NVM technology allows these devices to be immune from Single Event Upset (SEU) configuration failures.
  • In-circuit re-programmability, allowing for efficient product development and economical field updates.
  • Proven design security.
  • Low Power, up to 50 percent lower operating current than SRAM FPGAs.

Math Blocks and Logic Elements

PolarFireTM, SmartFusion®2, and IGLOO®2 devices share the same logic elements and math blocks.

Logic Block

Logic Block

  • Fully permutable four-input Look Up Table (LUT)
  • Separate flip-flop, which can be used independently of the LUT
    • Configurable as a register or latch
    • Asynchronous and synchronous load
    • Clock enable

Math Block

Math Block

  • Built-in addition, subtraction, and accumulation units.
  • Supports 18 X 18 signed and 17 X 17 unsigned multiplication.

Consult the datasheet for the specific device you are using to find the number of logic and math blocks, as well as the available, interconnect resources between the blocks.

Libero® Design Suite - A unified Integrated Development Environment (IDE)

Libero is Microchip's easy-to-use Graphical User Interface (GUI) based IDE for developing all our FPGAs. Libero provides all the essential FPGA and SoC design features including:

  • Design Entry: inputting the design into the IDE.
  • Simulation: verification of function and correctness of the design.
  • Synthesis: converting the design to logic and math blocks.
  • Constraint Setting: entering the timing and power requirements for the design.
  • Place and Route: mapping synthesized design into the selected device's math and logic block and selecting the interconnects between the blocks. Libero's place and route function use the design constraints to ensure the most time-critical paths are placed and routed first.
  • Timing and Power Analysis: verifying the constraints were achieved or exceeded on the post-route design.
  • Programming: downloading the bitstream into the FPGA.
  • In-Circuit Debugging: verifying the operation on the silicon.

Royalty-Free IP for use on Microchip FPGAs

Microchip has developed an array of IP modules optimized for operation on our FPGAs using Libero. The portfolio includes bus interfaces, memories, processors, encryption, Digital Signal Processor (DSP) functions, communication processors, and other peripherals.

A complete list, including descriptions, datasheets, and download links of this rapidly growing IP family is available on the "FPGA IP Core Tools" page.

Size, Speed, and CPU Differences

While the IGLOO2, SmartFusion2, and PolarFire FPGAs share architectural features, they address different design needs.

Speed and Size

IGLOO2 and SmartFusion are built using a 65 nm lower power flash memory process. PolarFire is built on a much faster 28 nm Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory process. Due to the advantages of the SONOS process, PolarFire devices are larger and can run faster than either IGLOO2 or SmartFussion2 FPGAs.

FeaturesSmartFusion2 / IGLOO2PolarFire
Family Members74
Logic Elements6K - 150K100K - 480K
Math Units2401480
Max RAM5 Mb33 Mb
Transcievers1 - 5 Gbps
PCIe Gen 2 Endpoints
250 Mbps - 12.7 Gps
PCIe Gen 2 Endoints or Root Port
I/O Speeds667 Mbps DDR3
750 Mbps LVDS
1600 Mbps DDR4
1.6 Gbps LVDS
On-Board Flash Memoryupto 523 KB NVM56KB secure NVM

Embedded CPUs

Many FPGA applications benefit from incorporating a CPU inside of the FPGA. These CPUs can either be "hard" or "soft" implementation.

  • Hard CPUs consist of circuitry added to the die. Hard CPUs do not consume any of the logic or math blocks. The maximum system clock frequency of hard CPU is determined when the chip is designed and specified in the device datasheet.
  • Soft CPUs are synthesized designs residing on some of the device's logic and math blocks. The frequency of a soft CPU depends upon the place and routing of the CPU portion of the netlist and may vary from application to application.
CortexTMM3HardYES166 MHz
RISC-VSoftYESYESYESAHB and AXI bus variants available
CoreABCSoftYESYESYESAssembly Language Only