Programming the Peripheral Trigger Generator

Last modified by Microchip on 2023/11/10 11:07

Establishing Step Command Timing

When setting up the clock controlling the execution speed of the Peripheral Trigger Generator (PTG) Step Commands, three parameters need to be considered:

  1. The signal used as the base clock source for the PTG Module.
  2. The number of clock periods needed for each Step Command cycle (prescaler).
  3. Whether or not the sequence will need to extend the clock cycle (step delay timer).

Image Showing PTG Clock Selection Mux

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Clock Source and Prescaler

The PTG Control Register (PTGCON) controls the clock source and the prescale value for the PTG module. There are six signals which can be set as the PTG clock. Once the clock has been determined, the application can divide the clock by a value between 1 and 32.

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PTGCON: PTG Control Register

PTG Control Register Bit Definitions

bit 15-13

PTGCLK<2:0>: Select PTG Module Clock

111 = Reserved
110 = Reserved
101 = Clock source will be T3CLK
100 = Clock source will be T2CLK
011 = Clock source will be T1CLK
010 = Clock source will be ADC FRC clock
001 = Clock source will be Fosc
000 = Clock source will be Fp

bit 12-8

PTGDIV<4:0>: PTG Clock module Prescaler (Divider) value

11111 = Divide by 32
11110 = Divide by 31
0001 = Divide by 2
0000 = Divide by 1

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Selecting the PTG Clock and Prescaler Using the MPLAB® XC16 C Compiler

// include the XC header file to define all register and bit names
#include <xc.h>

//  Select Fosc as the clock, with prescaler of 10
PTGCLK = 1;        // clock source set to Fosc
PTGDIC = 0x09;      // set prescaler to 10

// Select FP as clock source with NO prescaler
PTGCLCK = 0 ;       // clock source set to Fp
PGTDIV = 0 ;        // set prescaler to 1

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Delaying PTG Step Cycle

Using the PTG Step Delay Limit register (PTGSDLIM) causes the Step Commands lot to execute at a slower rate than the period set by PTGCON. When enabled, PTGSDLIM acts as a second prescaler for the PTG Module. The PTG clock will be divided by the value of PTGSDLIM. The use of the step delay timer is optional, as it can be enabled or disabled at runtime by using the PTGCTRL Step Command.

  • PTGCTRL with <OPTION> = 0b0010 (2) Disables the Step Delay.
  • PTGCTRL with <OPTION> = 0b0110 (6) Enables the Step Delay.
// include the XC header file to define all register and bit names
#include <xc.h>

//  Load Step Delay Limit register
PTGSDLIM = 4;    

// Sample Step Queues
_STEP0 =   PTGWHI | 0;  
_STEP1 =   PTGCTRL |  6;  // enable Step Delay
_STEP2 =   PTGWHI | 1;    // wait for external trigger
_STEP3 =   PTGIRQ | 0;    // generate PTG interrupt request
_STEP4 =   PTGCTRL | 2;   // disable Step Delay
_STEP5  =  JMP | 0;       // go to Step0 (i.e. repeat loop)

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Loading Step Commands into the Queue

Step commands are executed from the PTG Step queue. The Step queue is a set of 16-bit wide Special Function Registers (SFRs). The number of entries in the queue varies depending on which MCU is being used. The SFRs in the queue are PTGQUE0 through PTGQUEn (where n = ( # of Step commands/2 ) - 1). Two 8-bit wide Step Commands are loaded into each 16-bit wide Step queue SFR.

Step Commands Loaded into PTG Queue

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Compiler Supplied #defines

The Step queue is loaded with a series of assignment statements. When <xc.h> is included in a project the MPLAB® XC16 compiler provides easy-to-read definitions for the individual queue entries (e.g., _STEP0, _STEP1, etc..). The compiler definitions ensure the proper placement of Step Commands.

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Application #defines

A common mechanism used in application programs is to #define the commands in such a way as to make the loading of the queue more readable. Using this mechanism the #define includes the numeric opcode left shifted by four bits. Combined with the numeric for the OPTION field, this mechanism allows you to easily see what has been loaded into the queue.

Using #defines to Name Step Commands

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Enabling and Starting the PTG

In order for the PTG to begin executing step commands, two separate actions must be taken by the application:

  1. The PTG must first be enabled.
  2. Once enabled, the PTG will begin operating when it is started.

Enabling and starting the PTG are accomplished by writing to the PTG Control and Status (PTGCST) register.

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PTGCST: PTG Status and Control Register

PTG Status and Control Register Bit Definitions

bit 15

PTGEN: Module Enable bit

1 = Enables the PTG module
0 = Disables the PTG module

bit 7

PTGSTRT: Start PTG Sequencer bit

1 = Starts to sequentially execute Step commands
0 = Stops executing commands

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Examples of Enabling/Starting the PTG Using the MPLAB XC16 C Compiler

// include the XC header file to define all register and bit names
#include <xc.h>

PTGEN = 1;     // enables the PTG Module
PTGEN = 0;     // disables the PTG Module
PTGSTRT = 1;   // starts Step command executions
PGTSTRT = 0 ;  // stops execution

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Notes to Remember on Enabling and Starting the PTG:

  • At reset, the PTG module is Disabled and Stopped.
  • PTGCST is the only PTG Special Function Register (SFR) that can be written while the PTG Module is enabled. To modify any other PTG SFR, you must first disable the PTG by clearing PTGEN.
  • When PTGEN is set, the PTG Queue Pointer Register (PTGQPTR) is set to point to the first entry in the Step Queue. Starting and stopping PTG execution has no effect on PTGQPTR.

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