Initializing the Peripheral Trigger Generator

Last modified by Microchip on 2023/11/10 11:07

To initialize the PTG the following steps should be considered:

Initialize the MCU Peripherals

The Peripheral Trigger Generator (PTG) coordinates and sequences events between selected peripherals. The PTG works with the Analog-to-Digital Converter (ADC), the Output Compare/Pulse-Width Modulation (PWM) module, all General Purpose Timers, and the MCU's Interrupt Controller.

The mechanisms used to coordinate peripheral activities are triggers and Interrupt Requests (IRQs). The PTG can be programmed to either output a trigger, or to generate a PTG IRQ, based upon a trigger received from another peripheral. Successful sequencing depends upon careful coordination of the initialization of the PTG and PTG-monitored peripherals. Peripherals used in PTG sequences must be programmed to accept the appropriate PTG trigger(s) and, when needed, send a trigger to the PTG.

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Example of Coordinating Trigger Assignments

The PTG on the dsPIC33EP256GP506 is capable of sending a trigger to the Output Compare (OC) module. This PTG-generated trigger can serve as the OC module's clock or sync signal. The OC module can also generate a trigger signal for the PTG to monitor. The OC module generated trigger is seen by the PTG as either OC1 or OC2 trigger.

An Output Compare Module can either use the PTG Trigger as clock or sync source or can supply the PTG with a trigger source on OC match

To allow a PTG generated trigger to be the clock source for the OC module, OCxCON1 must be programmed.

Selecting PTG output as Output Compare clock by setting OCTSEL bits of OCxCON1 Register to 101

OCxCON2 can be programmed to allow a PTG generated trigger to synchronize the OC module. For sequences in which the PTG generates IRQ, it is imperative that the MCU's interrupt controller be initialized so that the PTG IRQs are enabled.

Setting SYNCSEL bits in OCxCON2 Register to 01010 allows PTG trigger to sync the Output Compare

Please consult the datasheet for the MCU you are using to verify the initialization requirements.

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Accessing PTG Registers

In addition to the registers needed to implement the queue, the Peripheral Trigger Generator (PTG) is controlled by twelve Special Function Registers (SFRs). Although initializing twelve SFRs may appear a daunting task, it is important to realize that not all of the SFRs may need to be initialized. The default settings for the PTG SFRs are non-intrusive. If an SFR controls a parameter not specifically used in a sequence, that SFR does not need to be initialized for the sequence to execute properly.

The PTG SFRs are divided into five categories:

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Control and Status Registers

PTGCSTProvides overall control and status reporting for the PTG, including Enable/Disable, Start/Stop, and Trigger output type (Toggle or Pulse). This is the only register that can be accessed while the PTG is enabled.
PTGCONDetermines the values used for many of the PTG timing parameters such as the clock source, any prescalers on the clock, and the width of the output triggers when the triggers are in Pulse mode. This register also controls the value of the PTG's Watchdog timer which limits the time the PTG will wait for a trigger.

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Limit Registers

PTGT0LIMDetermines the limit value for PTG Timer 0. Used by PTGCTRL to delay or pause the sequence.
PTGT1LIMDetermines the limit value for PTG Timer 1. Used by PTGCTRL to delay or pause the sequence.
PTGSDLIMSets the number of PTG clock cycles allocated to each step command. Using this register can slow down the speed in which PTG step commands are executed. The use of this Delay timer can be enabled or disabled with the PTGCTRL command.
PTGC0LIMUsed to specify the loop count for the PTGJMP0 command.
PTGC1LIMUsed to specify the loop count for the PTGJMP1 command

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Hold and Adjust Registers

PTGHOLDUsed by the PTGCOPY command, this register holds the value to be moved into one of the Limit registers or into the PTG Literal register (PTGL0).
PTGADJUsed by the PTGADD command, this register holds a value to be added to one of the Limit registers or the PTG Literal register (PTGL0).

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Literal and Broadcast Registers

PTGL0Holds a value to be written into the ADC1 channel select register (AD1CHS0). Only used by the PTGCTRL command. AD1CHS0 can also be written with the PTGSTRB command.
PTGBTEWhen the application wishes to simultaneously broadcast triggers to more than one peripheral (PTGCTRL command with OPTION = 0b1111), this register contains the list of triggers to generate.

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PTG Queue Registers

PTGQPTRPoints to the current step command being executed. When the PTG is enabled, this register is set to the first entry in the step queue.
These registers are the queue in which the step commands are located.

To prevent unintentional modifications to PTG operations caused by spurious writes to the PTG SFRs, the PTG Status and Control Register (PTGCST) is the only register that can be written to while the PTG is enabled. To modify PTG SFRs, other than PTGCST, you must ensure that the PTG is disabled (i.e. verify PTGCST<15> = 0).

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Initializing the Limit, Hold, and Adjust Registers

Limit Registers

Limit registers are used by step commands to control sequence timing.

PTGT0LIM and PTGT1LIM are used to insert one-time pauses into a sequence. The Peripheral Trigger Generator Control (PTGCTRL) step command has an option that will start either PTG Timer0 or PTG Timer1, then wait until the value of the timer equals the value of its Limit register. When the values are equal to each other, control is passed to the next step command in the queue.

The Step Delay Limit (PTGSDLIM) register is used to insert a temporary and repeatable delay for every step command in a sequence. The value loaded into PTGSDLIM is the number of PTG clocks needed to execute a single step command. When enabled, PTGSDLIM will cause the time period between successive step commands to be longer. When this register is disabled, all step commands will execute at the speed of the designated PTG clock. PTGSDLIM can be enabled or disabled using an option of the PTGCTRL step command.

PTGC0LIM and PTGC1LIM are loop counters for the conditional jump commands (PTGJMPC0 and PTGJMPC1). Using two loop counters allows a single level of nesting.

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Example of a Nested Loop Using the PTGCxLIM Registers

In this example, if PTGC0LIM = 3 and PTGC1LIM = 8, then the following commands would be executed before control is passed to the command in Step 5:

  • The step command loaded into Step 1 will execute 24 (3 x 8) times.
  • The step command loaded into Step 3 will execute 8 times.

Example of a Nested Loop in the PTG

  • All Limit registers can be initialized with a simple assignment statement when the PTG is disabled. For example, PTGSDLIM = 7.
  • During run-time, the value of any Limit register can be modified by the use of PTGCOPY or PTGADD step commands.

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Adjust Register

The PTGADD step command will add the value of the literal stored in PTGADJ to a Limit register. The particular Limit register to be modified is passed in the command's OPTION field. Modifying the Limit registers allows sequences to incrementally adjust the timing of generated triggers.

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Hold Register

The PTGCOPY step command moves the content of PTGHOLD into any of the Limit registers. PTGCOPY is typically used to reset a Limit register to its initial value after the register has been modified by PTGADD.

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Learn More

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